5nm IMEC ( VLSI 2016) 7nm Leti ( IEDM 2008 ) 10nm Stacked-NWs - - PowerPoint PPT Presentation

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5nm IMEC ( VLSI 2016) 7nm Leti ( IEDM 2008 ) 10nm Stacked-NWs - - PowerPoint PPT Presentation

Dec 15, 2022 1.61k likes •1.89k views

SCALING ROADMAP 5nm IMEC ( VLSI 2016) 7nm Leti ( IEDM 2008 ) 10nm Stacked-NWs (nanosheets) S. Barraud et al, session 17.6 Vertically Stacked- NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain |

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| 1

SCALING ROADMAP

10nm 7nm 5nm

Stacked-NWs (nanosheets)

IMEC ( VLSI 2016) Leti Devices Workshop | Maud Vinet | December 4th, 2016

  • S. Barraud et al, session 17.6 Vertically Stacked-

NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

Leti ( IEDM 2008)

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SLIDE 2

| 2 Leti Devices Workshop | Maud Vinet | December 4th, 2016

A Von Neumann processor can execute an arbitrary sequence

  • f

instructions on arbitrary data but the instructions and data must flow over a limited capacity bus connecting the processor and main memory.

Thus, the processor cannot execute a program faster than it can fetch instructions and data from memory.

VON NEUMANN PROCESSOR

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SLIDE 3

| 3 Leti Devices Workshop | Maud Vinet | December 4th, 2016

NEW COMPUTING PARADIGMS

Source: S Mitra, Stanford

1000x

Computation Immersed in Memory Massive parallelism Quantum computing

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SLIDE 4

Leti Devices Workshop | Maud Vinet | December 4th, 2016

WHICH DEVICES FOR NEW COMPUTING PARADIGMS?

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HIGH DENSITY 3D TECHNOLOGIES

Above 2x107vias/mm² demonstrated with CoolCubeTM Reachable 3D via pitch @ 14nm = 80nm

Leti Devices Workshop | Maud Vinet | December 4th, 2016

CoolCubeTM

Cu-Cu

3D Technologies: Several Disruptive Technologies to Look Ahead Dr Olivier Faynot

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SLIDE 6

| 6 Leti Devices Workshop | Maud Vinet | December 4th, 2016

CoolCubeTM

1. Top Junction Performance? 2. Inter Metal Interconnects? 3. Is It a Manufacturable Process? 4. Do You Really Benefit From the Lithographic Alignment?

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SLIDE 7

| 7 Leti Devices Workshop | Maud Vinet | December 4th, 2016

CoolCubeTM

1. Top Junction Performance? Same as bottom one (Pasini, VLSI 2015 and 2016) 2. Inter Metal Interconnects? 3. Is It a Manufacturable Process? 4. Do You Really Benefit from The Lithographic Alignment?

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WHAT ABOUT INTER LAYERS INTERCONNECTS?

Leti Devices Workshop | Maud Vinet | December 4th, 2016

Copper lines 500°

C

thermal stability proven

C Fenouillet, SSDM 2015

500°C 2h Line resistivity (Ohm.µm)

F Deprat, MAM 2016

Dielectrics Stability Demonstrated

500° C 2h 500° C 2h Thickness variation

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300mm WAFERS IN PRODUCTION FAB

L Brunet, VLSI 2016

No macroscopic bonding defects at 300mm wafer scale

Leti Devices Workshop | Maud Vinet | December 4th, 2016

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NANOMETRIC LITHOGRAPHY ALIGNMENT AT WAFER SCALE No Impact of Layer Deformation During Bonding and Thinning

L Brunet, VLSI 2016

Leti Devices Workshop | Maud Vinet | December 4th, 2016

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SLIDE 11

| 11 Leti Devices Workshop | Maud Vinet | December 4th, 2016

CoolCubeTM

  • Top Junction Performance
  • Inter Metal Interconnects
  • Manufacturable Process
  • Lithographic Alignment
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SLIDE 12

| 12 Leti Devices Workshop | Maud Vinet | December 4th, 2016

Opportunities for Logic and Non-Volatile Memory Co- Integration 2D TMD (TRANSITION METAL DICHALCOGENIDES)

  • A. KIS

Nanoletters 2014

  • S. Bertolazzi

ACS nano 2013

Memory

Spintronics Spin Logic with Ferromagnetic Memories Geim et al, Manchester team: ‘Graphene cake’ Quoc An Vu, Nature Comm, 2016

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SLIDE 13

| 13 Leti Devices Workshop | Maud Vinet | December 4th, 2016

2D TMD LARGE SCALE GROWTH

800°C

Low-temperature Atomic Layer Deposition of MoS2 using a novel organometallic precursor S. Cadot, et al, ALD 2015

ALD of MoS2

  • n SiO2
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SLIDE 14

| 14 Leti Devices Workshop | Maud Vinet | December 4th, 2016

NANOWIRES TO DESIGN QUANTUM DOTS

800°C

Wide Spacers over thin, undoped SOI

VGS h=1 h=2

pFET in the few-hole regime

h=0 VDS e=1 VGS e=0 e=2

nFET in the few-electron regime

FETs are Turned into Single Electron or Single Hole Transistor

  • V. Deshpande, IEDM 2012, M. Vinet IEDM 2013

10 nm

Quantum Electronic for Efficient Computing Dr Silvano de Franceschi

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SLIDE 15

| 15 Leti Devices Workshop | Maud Vinet | December 4th, 2016

Si SPIN QUBITS EXTEND NANOWIRES OPERATION Definition of a Two-Level System with Long Quantum Coherence

  • S. De Franceschi et al, 13.4 SOI Technology for

Quantum Information Processing (Invited)

  • R. Maurand et al., Nature Comm 2016
  • L. Hutin et al., VLSI Tech. Symp. 2016

Control of A Single Qubit: Initialization, Manipulation Communication Via Tunable Quantum Coupling Between Qubits

E field burst Vbg

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| 16 Leti Devices Workshop | Maud Vinet | December 4th, 2016

ROADMAP

Leti advanced technologies of today

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SLIDE 17

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2016 2020 2025

Leti Devices Workshop | Maud Vinet | December 4th, 2016

ROADMAP

Logic in memory Quantum Computing

  • M. Veldhorst et al., https://arxiv.org/pdf/1609.09700.pdf

Leti advanced technologies of today are supporting the shift in computing paradigms Neuromorphic computing

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SLIDE 18

Leti, technology research institute Commissariat à l’énergie atomique et aux énergies alternatives Minatec Campus | 17 rue des Martyrs | 38054 Grenoble Cedex | France www.leti.fr