28nm 8nm FDSOI DSOI Dig igit ital Desi esign Tut utorial orial - - PowerPoint PPT Presentation

28nm 8nm FDSOI DSOI Dig igit ital Desi esign Tut utorial

• rial

MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble ‐ France

Con Context & Motiv tivation tion

 Develop a digital design flow, based on standard methodologies and CAD tools  Detail each step of the digital flow: from RTL to GDSII  Plug an play tutorial (scripts and testbenches are delivered)  Provide a typical digital example (synchronous, sequential)  Propose the flow on an advanced CMOS technology: 28nm FDSOI  First version (1.4) sent in June 2015 to 166 institutions  Design‐Kit: CMOS28FDSOI 10ML, PDK 2.5.d  A new tutorial release is planned for Q1/Q2 2016  Design‐Kit: CMOS28FDSOI 10ML, PDK 2.5.f  New functionalities: body biasing, LVS and DRC verifications, etc…

Verilog RTL GDSII layout

CMP annual users meeting, 4 Feb. 2016, PARIS

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RT RTL to to GDS GDS flo flow

Verilog RTL Gate‐level Verilog netlist SDF timing annotation RC or DC Synthesis RC or DC Synthesis RTL simulation RTL simulation Test‐bench Gate‐level simulation Gate‐level simulation EDI Place & Route EDI Place & Route GDSII Physical layout Verilog netlist SDF timing back‐ annotation Back annotated simulation Back annotated simulation Calibre DRC Calibre DRC Calibre LVS Calibre LVS Test‐bench Test‐bench

CAD tools used in the tutorial are:

 Cadence Incisiv (NCSim)  Synopsys Design Compiler (DC)  Cadence RTL Compiler (RC)  Cadence Encounter (EDI)  Cadence Virtuoso, version 6.1.6  Mentor Graphics Calibre

F R O N T E N D B A C K E N D

CMP annual users meeting, 4 Feb. 2016, PARIS

DRC: Design Rules Checking LVS: Layout Versus Schematic

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FIR FIR cir circuit uit exa example

clk reset load in[15:0] eq

• ut[15:0]

TOP_FIR

clk reset load in[15:0]

• ut[15:0]

FIR_0 clk reset load in[15:0]

• ut[15:0]

FIR_15 clk reset load in[15:0] eq

• ut[15:0]

eqc

circuit called “TOP_FIR” 16 FIR filters in parallel

Simulation results:

Coefficients loading Outputs calculation Reset

FIR: Finite Impulse Response

CMP annual users meeting, 4 Feb. 2016, PARIS

Logic Logic sy synt nthesis

+

Testbench Gate level simulation Gate level simulation

Reset, loading and processing modes

CMP annual users meeting, 4 Feb. 2016, PARIS

Verilog RTL Gate level netlist RTL Compiler (Cadence)

• r

Design Compiler (Synopsys) Synthesis 5

Place Place and and ro route

Encounter Digital Implementation EDI (Cadence) Place and route Gate level netlist (+ top cell “PAD_TOP_FIR”) Verilog netlist GDSII layout

 IOs placement  Floorplan generation  Power‐plan  Core cells placement  Clock tree synthesis  Power routing  Final routing  SDF (timing generation)  Verilog netlist and GDS  STA (back‐annotation)

SDF: Standard Delay Format STA: Static Timing Analysis

CMP annual users meeting, 4 Feb. 2016, PARIS

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Sp Specific ific fe features in in 28nm 28nm FDSO FDSOI

 Meet particular DRC/ERC rules:

• WellTaps on all rows

(50µm spacing)

• Filler cells on top and bottom core rows

(OPC rules)  Restricting the tool to use the 8 first metal layers to route signals, and the 2 top layers for power.  Body biasing functionalities (detailed in next slide)

DRC: Design Rules Checking ERC: Electrical Rules Checking OPC: Optical Proximity Correcting

CMP annual users meeting, 4 Feb. 2016, PARIS

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Body Body bi biasi asing met methodol

• dology
• gy flo

flow

Body bias Body bias

Body biasing on LVT (flip‐well) transistors: Body biasing in layout view: GNDS VDDS GND VDD

Filler tap cell with separated power and ground rails: VDD/VDDS and GND/GNDS  FBB or RBB: speed or leakage optimization

FBB: Forward Body Biasing RBB: Reverse Body Biasing

CMP annual users meeting, 4 Feb. 2016, PARIS

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Body Body bi biasi asing met methodol

• dology
• gy flo

flow

External VDDS and GNDS voltages to core cells: 1) External VDDS/GNDS  I/O pads  Specific library supporting FBB and RBB (‐1,8V to +1,8V supply voltage) 2) IO pads  dedicated power rings 3) Power rings  power stripes 4) Power stripes  filler cells

Fillers row

GNDS VDDS

 Each row of functional cells is supplied

VDDS GNDS GNDS VDDS

CMP annual users meeting, 4 Feb. 2016, PARIS

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FBB: Forward Body Biasing RBB: Reverse Body Biasing

Final Final ve verificat cations

 GDSII and netlist imported under Cadence Virtuoso: as layout and schematic views  LVS and DRC verifications (on Calibre from Mentor Graphics or PVS from Cadence)

• When LVS and DRC succeed, the “TOP_FIR” circuit could be manufactured…!

DRC: Design Rules Checking LVS: Layout Versus Schematic

CMP annual users meeting, 4 Feb. 2016, PARIS

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Tu Tutorial deliv livery

 166 institutions received in June 2015 a first version of the tutorial  A new tutorial release is planned for Q1/Q2 2016, integrating new functionalities:

• body biasing (forward and reverse

body biasing),

• LVS and DRC verifications,
• wire bonding pads,
• SRAM block

 Already positive feedback from several designers !  Expected more digital designs in future MPW runs…

DRC: Design Rules Checking LVS: Layout Versus Schematic MPW: Multi‐Project Wafers

CMP annual users meeting, 4 Feb. 2016, PARIS

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Thank Thank yo you!