Low Power Multicore Architecture Using FDSOI Technology Marcello - - PDF document

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May 17, 2023 113 likes •213 views

7/15/2014 Low Power Multicore Architecture Using FDSOI Technology Marcello Coppola STMicroelectronics Agenda 2 FDSOI STNOC with FDSOI Application example Conclusions 1 7/15/2014 FD-SOI Speed & Energy Efficiency

SLIDE 1

7/15/2014 1

Low Power Multicore Architecture Using FDSOI Technology

Marcello Coppola STMicroelectronics

Agenda

FDSOI
STNOC with FDSOI
Application example
Conclusions

SLIDE 2

7/15/2014 2

FD-SOI Speed & Energy Efficiency

June 2014 4

Faster, Cooler, Simpler technology Enhanced design options

gives your SOC competitive advantages

FD-SOI transistors up to 30%

faster than bulk

Outstanding power efficiency

at every level

Extensive use of existing fab

infrastructure

Back-biasing as a flexible and

powerful optimization

Very large operating range for

the same design

Ultra-wide range DVFS

Mature process & ecosystem

Ecosystem ready at all stage:

wafer supply, design and manufacturing

Extended IP offer
PDK is available now
Strategic collaboration between

Samsung and ST

SLIDE 3

7/15/2014 3

STNoC at a glance

STNoC is a hardware/software set of Services on top of a distributed on-chip network

Main hardware building blocks are: Link, Router, Netw ork I nterfaces STNoC tool framework: I NoC

Source: Design of cost efficient Interconnect processing unit: Spidergon STNoC, ISBN: 9781420044713 5

STNoC Architecture

Vana ctrl regs body biased region under Varm vbbn/ vbbp Bo Body-Bias ge gene nerato tor 6 PLL PLL 0 1.3V

Network Interface

SLIDE 4

7/15/2014 4

STNoC: Multiple Body Biasing Regions

7 June 2014 GPU USB Video Blitter SATA DDR DDR R Core A DMAs X X X X X AL AL AL AL PCM Audio AL Core B 0 1.3V 0 1.3V 0 1.3V

“DRIVERS” FOR SMART CAR

8 Presentation Title

Safety & ADAS

Car access

EV Infotainment

Car2Infrastructure Car2Car

Autonomous Car

SLIDE 5

7/15/2014 5

9 Presentation Title

NEEDS FOR POWERFUL ENGINE

Expanding senses leads to smartness, which requires big brain
Exponential increase in computing performance requirement

Real time fusion of sensory multiple inputs i.e visual, radar, lidar, sensors, GPS and digital mapping Complex algorithms (Embedded Vision) for visual inputs analysis & interpretation i.e feature extraction, description, night vision…

Multicore Architecture

10 15/07/2014 Presentation Title

Full Cache Coherent IO Coherent and Not Coherent

SLIDE 6

7/15/2014 6

Dashboard Application Requirements

Activation periods of real-time tasks around 2ms for the rendering and

motor control,

Extreme cold boot time: system available 1.8 s after power-‐on
High-‐data throughput (through Ethernet and image processing pipe)
Low- jitter and low-‐latency behavior (<100ms)
Software frameworks: OpenGL ES

Boot Time Optimization

Speed
Optimize for target processor
Use faster medium for loading

primary, secondary boot loaders and kernel.

Reduce number of tasks leading to

the boot.

Remove features that are not

required

Use FDSOI

SLIDE 7

7/15/2014 7

Forward Body Biasing (FBB)

An extremely powerful and flexible concept in FD-SOI to :
Boost performance
Optimize passive and dynamic power consumption
Cancel out process variations and extract
ptimal behavior from all parts

13 0  1.3V

A very reasonable effort for extremely worthwhile benefits

FBB Vdds=-1.1, gnds=1.1 : Speed Up

FBB conditions offer

an evident advantage in speed (100 to 150 MHz advantage at the same Vdd).

Applying FBB at the

top available Vdd will provide a performance boost on the STNoC of about 23%

CMOS028 FDSOI

Target Frequency: 650 MHz
Conditions: ss_1V_125C

SLIDE 8

7/15/2014 8

Conclusions

FDSOI is an innovative and cheaper technology
STNoC takes advantages from FDSOI
Faster speed
Less number of gates
Mixed Critical applications (such as Automotive ones) can get

intrinsic benefits

Booting time can be reduced by 23%
Real Time support

15 16 June 2014 Advances in FD-SOI design for power optimization

Activity funded by

Q A

&

In collaboration with