Today: Machine Programming I: Basics History of Intel processors and architectures C, assembly, machine code Machine-Level Programming I: Basics Assembly Basics: Registers, operands, move Arithmetic & logical operations CSci 2021: Machine Architecture and Organization September 24th-28th, 2018 Your instructor: Stephen McCamant Based on slides originally by: Randy Bryant, Dave O’Hallaron 1 2 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Intel x86 Processors Intel x86 Evolution: Milestones Dominate laptop/desktop/server market Name Date Transistors MHz 8086 1978 29K 5-10 Evolutionary design First 16-bit Intel processor. Basis for IBM PC & DOS Backwards compatible up until 8086, introduced in 1978 1MB address space Added more features as time goes on 386 1985 275K 16-33 First 32 bit Intel processor , referred to as IA32 Added “flat addressing”, capable of running Unix Complex instruction set computer (CISC) Many different instructions with many different formats Pentium 4E 2004 125M 2800-3800 First 64-bit Intel x86 processor, referred to as x86-64 But, only a subset encountered with Linux programs Matches performance of more modern Reduced Instruction Set Core 2 2006 291M 1060-3500 Computers (RISC) First multi-core Intel processor In terms of speed. Less so for low power consumption. Core i7 2008 731M 1700-3900 Four cores 3 4 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Intel x86 Processors, cont. 2015 State of the Art Core i7 Broadwell 2015 Machine Evolution 386 1985 0.3M Pentium 1993 3.1M Desktop Model Pentium/MMX 1997 4.5M 4 cores PentiumPro 1995 6.5M Integrated graphics Pentium III 1999 8.2M 3.3-3.8 GHz Pentium 4 2001 42M 65W Core 2 Duo 2006 291M Core i7 2008 731M Server Model Added Features 8 cores Instructions to support multimedia operations Integrated I/O Instructions to enable more efficient conditional operations 2-2.6 GHz Transition from 32 bits to 64 bits 45W More cores 5 6 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 1
x86 Clones: Advanced Micro Devices Intel’s 64-Bit History (AMD) 2001: Intel Attempts Radical Shift from IA32 to IA64 Historically Totally different architecture (Itanium) AMD has followed just behind Intel Executes IA32 code only as legacy A little bit slower, a lot cheaper Performance disappointing Then 2003: AMD Steps in with Evolutionary Solution Recruited top circuit designers from Digital Equipment Corp. and x86- 64 (now called “AMD64”) other downward trending companies Intel Felt Obligated to Focus on IA64 Built Opteron: tough competitor to Pentium 4 Developed x86-64, their own extension to 64 bits Hard to admit mistake or that AMD is better 2004: Intel Announces EM64T extension to IA32 Recent Years Extended Memory 64-bit Technology (now called “Intel 64”) Intel got its act together Almost identical to x86-64! Leads the world in semiconductor technology AMD has fallen behind All but lowest-end x86 processors support x86-64 But, lots of code still runs in 32-bit mode Spun off its semiconductor factories 7 8 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Our Coverage Today: Machine Programming I: Basics IA32 History of Intel processors and architectures The traditional x86 C, assembly, machine code For 2021: RIP, Summer 2015 Assembly Basics: Registers, operands, move Arithmetic & logical operations x86-64 The standard cselabs> gcc hello.c cselabs> gcc – m64 hello.c Presentation Book covers x86-64 Web aside on IA32 We will only cover x86-64 9 10 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Assembly/Machine Code View Definitions CPU Memory Addresses Architecture: (also ISA: instruction set architecture) The Registers parts of a processor design that one needs to understand Code Data PC Data or write assembly/machine code. Condition Stack Instructions Examples: instruction set specification, registers. Codes Microarchitecture: Implementation of the architecture. Examples: cache sizes and core frequency. Programmer-Visible State PC: Program counter Memory Code Forms: Machine Code: The byte-level programs that a processor executes Address of next instruction Byte addressable array On x86-64, called “RIP” Code and user data Assembly Code: A text representation of machine code Register file Stack to support procedures Heavily used program data Condition codes Example ISAs: Store status information about most recent Intel: x86, IA32, Itanium, x86-64 arithmetic or logical operation ARM: Used in almost all smartphones Used for conditional branching 11 12 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 2
Turning C into Object Code Compiling Into Assembly Code in files p1.c p2.c C Code (sum.c) Generated x86-64 Assembly Compile with command: gcc – Og p1.c p2.c -o p long plus(long x, long y); sumstore: pushq %rbx Use basic optimizations ( -Og ) [New since GCC 4.8] movq %rdx, %rbx void sumstore(long x, long y, Put resulting binary in file p long *dest) call plus { movq %rax, (%rbx) text C program ( p1.c p2.c ) popq %rbx long t = plus(x, y); *dest = t; ret Compiler ( gcc – Og -S ) } Asm program ( p1.s p2.s ) text Obtain (on Ubuntu 14.04 machine) with command Assembler ( gcc or as ) gcc – Og – S sum.c Produces file sum.s binary Object program ( p1.o p2.o ) Static libraries ( .a ) Note : You may get different results on different machines Linker ( gcc or ld ) (older Linux, Mac OS X, …) due to different versions of gcc binary Executable program ( p ) and different compiler settings. 13 14 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Assembly Characteristics: Data Types Assembly Characteristics: Operations “Integer” data of 1, 2 , 4, or 8 bytes Perform arithmetic function on register or memory data Data values Addresses (untyped pointers) Transfer data between memory and register Load data from memory into register Floating point data of 4, 8, or 10 bytes Store register data into memory Code: Byte sequences encoding series of instructions Transfer control Unconditional jumps to/from procedures Conditional branches No aggregate types such as arrays or structures Just contiguously allocated bytes in memory 15 16 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Object Code Machine Instruction Example C Code Code for sumstore *dest = t; Assembler Store value t where designated by 0x0400595: Translates .s into .o dest 0x53 Binary encoding of each instruction 0x48 Assembly 0x89 Nearly-complete image of executable code movq %rax, (%rbx) Move 8-byte value to memory 0xd3 Missing linkages between code in different Quad words in Intel parlance 0xe8 files 0xf2 Operands: 0xff Linker t : Register %rax 0xff Resolves references between files dest : Register %rbx 0xff • Total of 14 bytes Combines with static run-time libraries 0x48 *dest : Memory M[ %rbx] • Each instruction 0x89 E.g., code for malloc , printf Object Code 1, 3, or 5 bytes 0x03 Some libraries are dynamically linked 0x40059e: 48 89 03 0x5b 3-byte instruction • Starts at address 0xc3 0x0400595 Linking occurs when program begins Stored at address 0x40059e execution 17 18 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition 3
Recommend
More recommend
