1 Recall MIPS word size In hex 31 30 29 28 27 26 25 24 23 22 21 - - PDF document

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1 Recall MIPS word size In hex 31 30 29 28 27 26 25 24 23 22 21 - - PDF document

Sep 08, 2023 280 likes •356 views

Stored program computer MIPS Memory Forms of Address (2 32 -1) . . . MIPS private regs PC (A+24) MIPS machine code and addressing IR (A+20) modes MIPS user regs (A+16) 0 0 0 0 $zero (A+12) $v0

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SLIDE 1

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CS240 Computer Organization Department of Computer Science Wellesley College

Forms of Address

MIPS machine code and addressing modes

Stored program computer

. . . (232-1) (A+8) (A+4) (A) (12) (8) (4) (0) MIPS Memory

MIPS

.

. . . PC IR $zero MIPS private regs 0 0 0 0 MIPS user regs $v0 $s0 $a0 $t0 $t1 $t2 . . . . . . . . . $s1 . . . (A+24) (A+20) (A+16) (A+12)

  • The numeric form of a computer’s instruction set is know

as its machine code.

  • Memory addresses can contain either integer data or

instructions represented in numeric form. How do we tell them apart?

  • MIPS machine code is a bit complicated, but not as

complicated as Lucy’s. 000000 10001 10010 01000 00000 100000

  • 32 bits or one word

Instruction, number, or string?

Machine code 7-3 Machine code 7-4

CISC / RISC

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SLIDE 2

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Recall MIPS word size

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 0 1 1

least significant bit most significant bit

7-5 Machine code

In hex

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 0 0 0 0 00 0 0 0 0 0 0 0 1 0 1 1

least significant bit most significant bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 29 B6 00 0B

7-6 Machine code

Machine code

What to do (operation code)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0

What to do it with*

0 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

7-7 Machine code

*Well, more or less.

Machine code 7-8

Assembling MIPS instructions

The MIPS assemble language instruction add

$t0, $s1, $s2

translates into the following machine code 000000 10001 10010 01000 00000 100000

  • 6 bits

5 bits 5 bits 5 bits 5 bits 6 bits

32 bits or one word

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SLIDE 3

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Machine code 2-9

MIPS instruction format*

  • p

rs rt rd shamt funct

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

instruction operation

  • r opcode

first register source operand second register source operand register destination

  • perand

shift amount (coming soon) function code *R-type (for register) or R-format.

Machine code 7-10

add $t0, $s1, $s2

000000 10001 10010 01000 00000 100000

  • 6 bits

5 bits 5 bits 5 bits 5 bits 6 bits

instruction operation

  • r opcode

first register source operand second register source operand register destination

  • perand

shift amount (coming soon) function code

Machine code 7-11

addi $t0, $s1, 1024*

001000 10001

  • 01000

00000

  • 6 bits

5 bits 5 bits 5 bits 5 bits 6 bits

instruction operation

  • r opcode

first register source operand second register source operand register destination

  • perand

shift amount (coming soon) function code *Doesn't fit!

Machine code 7-12

Design Principle 4. Good design demands good compromises

  • p

rs rt constant or address

  • 6 bits

5 bits 5 bits 16 bits still 32 bits

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SLIDE 4

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  • p

rs rt constant or address

  • 6 bits

5 bits 5 bits 16 bits

001000 10001 01000 0000 0100 0000 0000

  • 6 bits

5 bits 5 bits 16 bits

instruction operation

  • r opcode

first source register operand register destination

  • perand

immediate amount

addi $t0, $s1, 1024

register 8 register 17

Machine code 7-13 Machine code 7-14

Oompa Loompa Doompadee Doo*

  • p

rs rt constant or address

  • 6 bits

5 bits 5 bits 16 bits still 32 bits

  • Exercise. First compile and then assemble A[200] = h + A[300],

where we assume $t1 has the base address of A and $s2 corresponds to h.

*Here’s where that green card in the front of your text comes in handy.

Machine code 6-15

  • p

rs rt constant or address

  • 6 bits

5 bits 5 bits 16 bits still 32 bits

addi $t0, $s1, 16711685

Machine code 7-16

Dealing with larger constants

001111 00000 01000 0000 0000 1111 1111 lui $t0, 255 # $t0 is register 8 0000 0000 1111 1111 0000 0000 0000 0000

fills lower 16 bits with zeros transfers 16-bit immediate constant

register 8

*But what about the lower 16-bits?

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SLIDE 5

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Machine code 7-17

OR immediate to the rescue

001111 00000 01000 0000 0000 1111 1111 lui $t0, 255 # $t0 is register 8 0000 0000 1111 1111 0000 0000 0000 0000

transfers 16-bit immediate constant

register 8

  • ri $t0, $t0, 5

001101 01000 01000 0000 0000 0000 0101

OR of these two values goes into lower 16-bits of $t0

Machine code 7-18

lui $t0, 255 # $t0 is register 8

  • ri

$t0, $t0, 5 # or lower half with upper add $t0, $t0, $s1 # $t0 <- $s1 + 16711785

addi $t0, $s1, 16711685

  • Finally, the newly constructed binary value of 16711685 is added

to the contents of $s1 and stored in $t0.

  • The original pseudoinstruction is translated into three actually

assembly language instructions at assemble time.

Machine code 7-19

Hardware/Software interface

  • The MIPS assembler

takes care of breaking large constants into pieces and then reassembling them into a register.

  • A special register, $at, is

reserved for this task.

Machine code 7-20

J-type instruction format

000010 00 0000 0000 0000 0010 0000 0001 j 1025 # goto location 1025

6 bits 26 bits

  • p jump address

Program Counter (PC)

Memory

jump destination instruction :

26-bit destination is concatenated with upper 4 bits of PC.

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SLIDE 6

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Machine code 7-21

000101 10000 10001 address

  • 6 bits

5 bits 5 bits 16 bits still 32 bits

Conditional branches are more limited

bne $s0, $s1, address

Machine code 7-22

Elementary my dear Watson

  • Conditional branches are

found in “loops” and in “if” statements, so they tend to branch to a nearby location.

  • Since the PC contains the

address of the current location, we can branch to within 215 words of the current location using PC- relative addressing.

Machine code 7-23

PC-relative addressing

  • p rs rt offset

Program Counter Memory branch destination instruction

bne $t0, $s5,Exit

Machine code 7-24

Compare with base addressing

  • p rs rt offset

base register Memory word or byte operand

lw $t0, 12($t1)

  • p rs rt offset

Program Counter Memory branch destination instruction

bne $t0, $s5,Exit

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SLIDE 7

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Machine code 7-25

Branching offsets in machine language

while (save[i] == k) i += 1; address op rs rt rd shamt funct Loop: sll $t1, $s3, 2 80000 0 0 19 9 2 0 add $t1, $t1, $s6 80004 0 9 22 9 0 32 lw $t0, 0($t1) 80008 35 9 8 0 bne $t0, $s5, Exit 80012 5 8 21 2 addi $s3, $s3, 1 80016 8 19 19 1 j Loop

  • 80020 2 20000

Exit:

  • address or offset

Machine code 7-26

This week’s puzzler

  • Suppose we are given a

branch on register $s0 being equal to register $s1: beq $s0, $s1, L1

  • Replace this by instruction

(s) that offers a much greater branching distance.

Machine code 7-27

The five MIPS addressing modes

  • It is sometimes necessary

(when reading a core dump for example) to reverse engineer machine language into assembly.

  • What is the assembly

language statement corresponding to 00af8020?

Byte Halfword Word Registers Memory Memory Word Memory Word Register Register

  • 1. Immediate addressing
  • 2. Register addressing
  • 3. Base addressing
  • 4. PC-relative addressing
  • 5. Pseudodirect addressing
  • p

rs rt

  • p

rs rt

  • p

rs rt

  • p
  • p

rs rt Address Address Address rd . . . funct Immediate PC PC

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