1.3. MINOS KERNEL 79 System Startup OS Initializer (we!) RPI (2) - PowerPoint PPT Presentation

1.3. MINOS KERNEL 79

System Startup OS Initializer (we!) RPI (2) VC / firmware • Initialize hardware • Set stack registers for all processor modes • Copy boot image to RAM • Setup free heap list and module list • Jump to OS boot image (Initializer) • Initialize MMU & page table • Setup interrupt handlers & runtime vectors • Start timer & enable interrupts • Initialize other runtime data structures • Initialize UARTs • Initialize RAM disk • Enter scheduling loop on OS 80

Modular Kernel Structure The Big Picture Minos Command Interpreter and Scheduler Modules "imports" Dynamic Linker: Module Loader File Kernel Logging etc. I/O System Kernel Runtime floating point emulation, memory allocation … Memory Management Device Drivers 81

Modular Kernel Structure Minos Modules in More Detail OS User Interface Minos Command Interpreter and Scheduler Module Loader Modules Dynamic Linker: Module Loader File I/O System RamVolumes SerialLog Uart API abstract block device OFS abstract Tools Devices & concrete FS methods character device floating Kernel Runtime Tools point emulation Strings Log Kernel FPE Heaps memory UartMin Platform allocation 82 unit

Kernel Module  MODULE Kernel; Platform IMPORT SYSTEM, Platform; FPE64 TYPE … ARMRuntime (* types of runtime data structure *) Heaps VAR … UartMin (* global runtime data structures *) Kernel PROCEDURE P* (…); (* exported *) Utils BEGIN … Strings (* low level routine *) Device END …; Uart PROCEDURE … (…); (* internal *) Log (* low level routine *) SerialLog BEGIN … OFS END …; IFSRamVolumes BEGIN … Tools (* runtime initialization *) Streams END Kernel. Modules Minos 83

Memory Layout -- Objectives  As simple as possible 0xFFFFFFFF  Support null-pointer checks via MMU (4G-1)  Classical Heap / Stack layout  1 MB pages 0x40000000 devices 0x3F000000 VC 0x30000000 kernel.img 0x8000 0x0 84

Memory Layout: big picture 0xFFFFFFFF 0xFFFFFFFF 1MB (4G-1) 0xFFF00000 0x40000000 0x40000000 devices devices 1:1 (strongly ordered) 0x3F000000 0x3F000000 VC VC 0x30000000 0x30000000 (768 M) 1:1 kernel.img kernel.img 0x108000 initial stack 0x100000 kernel.img first 1 MB unmapped first 1 MB 0x0 virtual physical 85

Virtual Memory Layout: Heap, Stack, RAMDisk 0x30000000 RAM Disk (256M) 0x20000000 stack (16M) 0x1F000000 unmapped 0x1EF00000 heap (493 MB) 0x00200000 kernel.img 0x00108000 0x00100000 first 1 MB 0x00000000 virtual 86

Virtual Memory Layout: IRQ Table / MMU 64KB-64 unused Fast IRQ Adr 4B 1MB IRQ Adr 4B Not assigned 4B 0xFFF00000 Data Abort Adr 4B Prefetch Adr 4B SWI Adr 4B UNDEF Adr 4B RESET Adr 4B 0xFFFF0020 FIQ 4B Pipeline! IRQ 4B Not assigned 4B Data Abort 4B Prefetch Abort 4B SWI 4B UNDEF 4B LDR PC, [PC+0x18] RESET 4B 0xFFFF0000 encoded as hex number 359ff018 0xFFFEFFFF 16KB MMU Table 0xFFFEC000 0xFFFEBFFF 16KB UNDSP 0xFFFE8000 0xFFFE7FFF ABORT Stack 16KB 0xFFFE4000 0x00000000 0xFFFE3FFF virtual IRQ Stack 911KB 87 0xFFF00000

Initialization: Kernel (body) SYSTEM.LDPSR(u, src) [instruction MSR] u = 0 PSR of current processor mode u = 1 PSR of saved processor mode VAR lnk: PROCEDURE; src value to be loaded in PSR, an expression ... BEGIN (* do not enter any call here --> link register consistency ! *) store link register globally – we are switching the stack! SYSTEM.PUT32(ADDRESSOF(lnk), SYSTEM.LNK()); SYSTEM.LDPSR( 0, Platform.SVCMode + Platform.FIQDisabled + Platform.IRQDisabled ); SYSTEM.SETSP(Platform.SVCSP); disable IRQs, stay in SVC mode SYSTEM.SETFP(Platform.SVCSP); SYSTEM.LDPSR( 0, Platform.IRQMode + Platform.FIQDisabled + Platform.IRQDisabled ); SYSTEM.SETSP(Platform.IRQSP); new stack top for this mode 88

Initialization Kernel (body) SYSTEM.LDPSR( 0, Platform.FIQMode + Platform.FIQDisabled + Platform.IRQDisabled); SYSTEM.SETSP(Platform.FIQSP); ... SYSTEM.LDPSR( 0, Platform.SVCMode + Platform.FIQDisabled + Platform.IRQDisabled ); (* Disable interrupts, init SP, FP *) InitMMU; SetupInterruptVectors; InitHandlers; EnableIRQs; OSTimer; lnk continue execution (next body) END Kernel. 89

Initialization Heap Stack MODULE Heaps; heapEnd ... BEGIN heap heapStart := Platform.HeapBase; heapBase heap := Platform.HeapBase; heapEnd := Platform.HeapEnd; END Heaps. 90

Address Translation (1 MB pages) 0 31 20 19 4 K 1 M virtual Index Offset MMU lookup 0 31 20 19 4 K 1 M PhysAdr[20..31] PhysAdr[19..0] = Offset physical 91

Translation Table 0 31 4 K 2019 1 M virtual Index Offset translation table TranslationTableBase Index register Translation table (4k entries) 92

Page Table Entries 0 Possible entries: 31 20 19 4 K 1 M Index Offset virtual  Invalid translation table TranslationTableBase Index register 31 2 1 0 Ignored 0 0 Translation table (4k entries)  Section 31 20 19 16 15 14 12 11 10 9 8 5 4 3 2 1 0 S I TEX AP AP Section base address Domain P C B 1 0 0 S B M [2] [1:0] [2:0] Z 18 (Properties define memory type and sharing attributes)  Page table (2nd level: 4k or 64K pages), Supersection (16 MB pages) (cf. ARM v7-A Section B.3) (cf. ARM Reference Manual v7-A Section B.3)

Accessing the System Control Processor MCR (Move to Coprocessor from Arm Register) ARM Processor System MRC (Move to Arm Register from Coprocessor) MMU / MPU Control Processor coprocessor CPU Coprocessor number register registers coprocessor number 15 opcodes 94

System Control Processor Registers ARM Cortex A7 Architecture MPCore ARM ARM ARM ARM ARM ARM ARM ARM Reference Architecture Architecture Architecture Architecture Technical Architecture Architecture Architecture Architecture Manual ARM Reference Reference Reference Reference Reference Reference Reference Reference Reference v7A Manual ARM Manual ARM Manual ARM Manual ARM Manual Manual ARM Manual ARM Manual ARM Manual ARM v7, B4.1.154 v7, B4.1.154 v7, B4.1.154 v7, B4.1.154 v7, B4.1.154 v7, B4.1.154 v7, B4.1.154 v7, B4.1.154 B4.1.154 4.2.3. e.g. "MCR P15, 0, R0, C2, C0, 0 ; set page table base address" 95

Cache  ARM processors can support several levels of cache (from ARM Architecture Reference Manual ARM v7-A, Section A3.9.2 96

Cache Coherency Caches largely invisible to the application programmer in normal operation. Cache coherency breakdown: reads or writes reads or writes agent 1 cache memory agent 2 Examples:  agent 1 = processor, agent 2 = DMA controller relevant even for  agent 1 = processor ( instruction cache ), agent 2 = processor ( data cache ) single-core systems  agent 1 = processor x, agent 2 = processor y 97

Ensuring Cache Coherency  Not enabling caches in the system  RPI starts with MMU switched off and with caches disabled  Use memory maintenance operations to manage cache coherency issues in software  E.g. when sharing information between processors  E.g. when changing instruction memory from data path  Use hardware coherency mechanisms configurable for memory regions  E.g. strongly ordered memory for memory regions containing device registers 98

Memory types and attributes Memory type Shareable Other Objective attribute attribute attribute Strongly-ordered Shareable Memory accesses to Strongly-ordered memory occur in program order. Device Shareable Memory mapped peripherals that are shared by several processors. Non-Shareable Memory mapped peripherals that are used only by a single processor. Normal Shareable Non-cacheable Normal memory that is shared between Write-Through cacheable several processors. Write-Back cacheable Non-Shareable Non-cacheable Normal memory that is used only by a Write-Through cacheable single processor. Write-Back cacheable ... we will revisit this topic again when discussing memory ordering in the context of a multi- core kernel. 99

Cache properties (ARM v7)  Data memory cache: Reads and Writes from one observer to the same physical location, also from different virtual addresses, always happen in program order  No memory barriers required  Instruction caches are never written to or read from by memory load / store operations  The guarantees from above do not necessarily apply to instruction cache, depending on the cache implementation  Changing memory attributes in the page table can require a cache maintenance operation 100

Cache Coherency Issues Memory Location Update by a Processor not visible to other observers because 1. new updates are still in the writing's processor cache 2. cache of observer contains stale copy of the memory Two explicit mechanisms to address this Clean : updates made by a writer made visible to other observers that can access memory at the point to which the operation is performed. Invalidate : A cache invalidate operation ensures that updates made visible by writers that access memory are made visible to an observer that controls the cache. [precise definitions in ARM Architecture Manual v7, B 2.2.6] 101

Cache Maintenance  Instruction/Memory Cache can be selectively enabled / disabled  Cache manipulation: CRn = 7, TLB mainpulation: CRn = 8 clean data cache invalidate data / instruction cache, by set / way, by VA, ... 102