1 2 3 4 5 6 The Graphics Processing Unit is controlled by the - PDF document

The Graphics Processing Unit is controlled by the CPU through a direct interface of memory-mapped IO registers, and indirectly by parsing commands that the CPU has placed in memory. The display interface and blitter (block image transferrer) are controlled primarily by direct CPU register addresses, while the 3D and Media pipelines and the parallel Video Codec Engine (VCE) are controlled primarily through instruction lists in memory. 7

The Command Stream (CS) unit manages the use of the 3D and Media pipelines; it performs switching between pipelines and forwarding command streams to the currently active pipeline. It manages allocation of the URB and helps support the Constant URB Entry (CURBE) function. 3D Pipeline ne The 3D pipeline provides specialized 3D primitive processing functions. These functions are provided by a pipeline of “fixed function” stages (units) and GEN threads spawned by these units. Media a Pipeline ne The Media pipeline provides both specialized media-related processing functions and the ability to perform more general (“generic”) functionality. These Media-specific functions are provided by a Video Front End (VFE) unit. A Thread Spawner (TS) unit is utilized to spawn GEN threads requested by the VFE unit, or as required when the pipeline is used for general processing. See Media Pipeline Overview. Subsys ystem The Subsystem is the collective name for the GEN programmable cores, the Shared Functions accessed by them (including the Sampler, the DataPort, and the Inter-Thread Communication (ITC) Gateway), and the Dispatcher that manages threads running on the cores. 8

A shared function is implemented where the demand for a given specialized function is insufficient to justify the costs on a per-EU basis. Instead a single instantiation of that specialized function is implemented as a stand-alone entity outside the EUs and shared amongst the EUs. 11

There are two register files shown here:  General Register File (GRF) and  Message Register File (MRF). Instruction operands order: destination, source0, source1. 14

This mode is for first demonstration mainly. It is not widely used in practice. 15

JIP is in units of 64bit chunks (2 DWORDS). 22

1 2 3 4 5 6 The Graphics Processing Unit is controlled by the - PDF document

1 2 3 4 5 6 The Graphics Processing Unit is controlled by the CPU through a direct interface of memory-mapped IO registers, and indirectly by parsing commands that the CPU has placed in memory. The display interface and blitter (block image

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