XED:%EXPOSING%ON,DIE%ERROR% DETECTION%INFORMATION%FOR% - - PowerPoint PPT Presentation
XED:%EXPOSING%ON,DIE%ERROR% DETECTION%INFORMATION%FOR% STRONG%MEMORY%RELIABILITY Prashant%Nair,%Georgia%Tech Vilas&Sridharan ," AMD&Inc.&&&&& Moinuddin Qureshi,&Georgia Tech ISCA%43,)June)20 th 2016
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b
Aspect Ratio Aspect Ratio = H/b Aspect Ratio of Storage Node Technology Node (nm)
Source: S. J. Hong (Hynix), IEDM 2010 H
70 60 50 40 30 20 10 20 40 60 80 100
Figure 2: Exponential increase in aspect ratio of DRAM cells with scaling to smaller technology nodes (redrawn from [5])
[ArchShield ISCA’13,%CiDRA HPCA’15]
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Fault& Mode Transient& Fault Rate&(FIT) Permanent& Fault Rate&(FIT) Bit 14.2 18.6 Word 1.4 0.3 Column 1.4 5.6 Row 0.2 8.2 Bank 0.8 10 *Total 18 42.7
Sridharan et.%al.%SC13
b
Aspect Ratio Aspect Ratio = H/b Aspect Ratio of Storage Node Technology Node (nm)
Source: S. J. Hong (Hynix), IEDM 2010 H
70 60 50 40 30 20 10 20 40 60 80 100
Figure 2: Exponential increase in aspect ratio of DRAM cells with scaling to smaller technology nodes (redrawn from [5])
[ArchShield ISCA’13,%CiDRA HPCA’15]
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP CHIP
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP CHIP
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip CHIP
Fault& Mode Transient& Fault Rate&(FIT) Permanent& Fault Rate&(FIT) Bit 14.2 18.6 Word 1.4 0.3 Column 1.4 5.6 Row 0.2 8.2 Bank 0.8 10 *Total 18 42.7
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip CHIP
*Sridharan+*SC13 Fault& Mode Transient& Fault Rate&(FIT) Permanent& Fault Rate&(FIT) Bit 14.2 18.6 Word 1.4 0.3 Column 1.4 5.6 Row 0.2 8.2 Bank 0.8 10 *Total 18 42.7
CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip CHIP
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip CHIP
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP ECC Chip CHIP D0 D1 D2 D3 D4 D5 D6 D7 ECC
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 FAIL D3 D4 D5 D6 D7 PA
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Corrects? Detects? SingleWBit&Failures
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Corrects? Detects? SingleWBit&Failures
CRC,8%ATM,code%instead%of%Hamming,code
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP OnWDie&ECC&detected&it Reconstruct&Data&in&Failed&Chip
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 D2 D3 D4 D5 D6 D7 PA
FAIL
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 D2 D3 D4 D5 D6 D7 PA
Failed
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 D2 D3 D4 D5 D6 D7 PA
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 D2 D3 D4 D5 D6 D7 PA
OK OK FAIL OK OK OK OK OK OK
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 D2 D3 D4 D5 D6 D7 PA
OK OK FAIL OK OK OK OK OK OK
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP
D0 D1 CW D3 D4 D5 D6 D7 PA 64(bits
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Yes
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP
D0 D1 CW D3 D4 D5 D6 D7 PA
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 CW D3 D4 D5 D6 D7 PA 64(bits
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 CW D3 D4 D5 D6 D7 PA
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 CW D3 D4 D5 D6 D7 PA
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 CW D3 D4 D5 D6 D7 PA 64(bits
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP D0 D1 CW D3 D4 D5 D6 D7 PA
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP
D0 D1 CW D3 D4 D5 D6 D7 PA 64(bits
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP
D0 D1 CW 3 D3 D4 D6 D7 PA 64(bits CW 5 64(bits
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP
D0 D1 CW 3 D3 D4 D6 D7 PA 64(bits D5 No(SDC,(No(DUE
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CHIP CHIP CHIP CHIP CHIP CHIP CHIP Parity Chip CHIP
D0 D1 CW 3 D3 D4 D6 D7 PA 64(bits CW 5 64(bits
SDC((10>6),(DUE((10>13)
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*,Nair,et.,al.,HiPEAC 2016
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10-5 10-4 10-3 10-2 10-1 1 2 3 4 5 6 7
Probability of System Failure (Log Scale) Years
SECDED: ECC-DIMM ChipKill XED
43x 4x
(9 Chips) (9 Chips) (18 Chips)
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0.9 1 1.1 1.2 1.3 SECDED XED CHIPKILL
Normalized& Execution&Time
21%
Lower%the%better
0.8 1 1.2 1.4 SECDED XED CHIPKILL
Lower%the%better
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0.9 1 1.1 1.2 1.3 SECDED XED CHIPKILL
Normalized& Execution&Time
21%
Normalized Memory&EnergyWDelay&Product (EDP)
34%
Lower%the%better
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“You(are(in(a(pitiable(condition,(if(you(have(to(conceal(what(you(wish(to(tell” W Publilius Syrus
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Table IV SDC AND DUE RATE OF XED
Memory Power Execution Time
Chipkill Chipkill Chipkill Double Chipkill Normalized Value
Expose On−Die ECC using Additional Transaction Expose On−Die ECC using an Extra Burst
0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 Double
SPEC PARSEC BIOBENCH COMM GMEAN