When (Low ) Pow er Really Matters When (Low ) Pow er Really Matters - - PowerPoint PPT Presentation

When (Low ) Pow er Really Matters When (Low ) Pow er Really Matters When (Low ) Pow er Really Matters When (Low ) Pow er Really Matters

Yogesh K. Ramadass, AnanthaGroup Microsystems Technology Laboratory

Outline Outline Outline Outline

Introduction Voltage Scaling techniques Challenges with Low voltage operation System Examples Conclusion

Moore Moore Moore Moore ’ ’s Law s Law s Law s Law

• No. of transistors doubles every two years

Not a physical law, started of as a graphical observation Exponential increase in circuit complexity

Gordon Moore Co-founder, INTEL

Processor Pow er Levels Processor Pow er Levels Processor Pow er Levels Processor Pow er Levels

More Speed More Power More Processing More Power

So Where is the Pow er Lost? So Where is the Pow er Lost? So Where is the Pow er Lost? So Where is the Pow er Lost?

Analog Circuits – Opamps, ADC/DAC’s, Current/Voltage

references

Bias Currents Switches

Digital Circuits – Processors, Memory

Charging up capacitances

Leakage!!

Imagine burning calories when sitting idle 30% of total power in big microprocessors More on this later

A simplistic view of process scaling A simplistic view of process scaling A simplistic view of process scaling A simplistic view of process scaling

VBAT CL

Reduce CL , reduce power Area reduces too!!

Area = Cost

Faster switches

More processing

Downside, switches don’t turn off completely

250, 180, 130, 90, 65, 45, 32, 22 Process Scaling enables Moore’s Law

s 2 BAT L 2 BAT L cycle

f V C Power V C E . = =

( )

BAT L 2 T BAT s

V C V V f . − ∝

Outline Outline Outline Outline

Introduction Voltage Scaling techniques Challenges with Low voltage operation System Examples Conclusion

Dynamic Voltage Scaling Dynamic Voltage Scaling Dynamic Voltage Scaling Dynamic Voltage Scaling

Goal: Operate Circuits at just enough voltage

• B. Calhoun
• B. Calhoun

( )

BAT L 2 T BAT s

V C V V f . − ∝

Implementation of a DVS System Implementation of a DVS System Implementation of a DVS System Implementation of a DVS System

• V. Gutnik
• V. Gutnik

1996 1996

Change Voltage with change in workload

Pow er Savings by DVS Pow er Savings by DVS Pow er Savings by DVS Pow er Savings by DVS

Courtesy : intel.com Exponential drop both voltage and frequency scale Linear drop only frequency scales, min. voltage Power (Normalized)

Intel Core Duo Processor

Energy Constrained Applications Energy Constrained Applications Energy Constrained Applications Energy Constrained Applications

Micro-sensor networks RFID Tags Medical devices Portable Electronics

Target Tracking & Detection (Courtesy of ARL)

Inductive Link Inductive Link Inductive Link Inductive Link

Try to reduce power consumption to fit in energy budget

Sub-threshold Operation: slower, minimum energy Strong Inversion Operation: fast, high-energy

0.2 0.4 0.6 0.8 1 10

• 8

10

• 6

10

• 4

10

• 2

100

VDD (Normalized) ID (Normalized)

Sub-threshold logic operates with VDD < VT Both on and off current are sub-threshold “leakage”

Sub Sub Sub Sub-

• threshold Operation

threshold Operation threshold Operation threshold Operation

D

I Speed ∝

Minimum Energy Point (MEP) Minimum Energy Point (MEP) Minimum Energy Point (MEP) Minimum Energy Point (MEP)

LEAKAGE ACTIVE TOTAL

E E E + =

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + = + =

−

th DD

nV V eff eff D D OFF DD

e L C T V I CV

2 DD 2

V

65nm simulation

for 7-tap FIR filter showing minimum energy

• peration

Leakage Energy Total Energy Active Energy MEP

0.2 0.4 0.6 0.8 1 1.2 0.5 1 1.5 2 2.5 3 3.5 4

VDD (V) Eop (Normalized)

Motivation Motivation Motivation Motivation – – Minimum Energy Tracking Minimum Energy Tracking Minimum Energy Tracking Minimum Energy Tracking

Minimum Energy Point (MEP) varies with workload and

temperature

MEP moves when ratio of active to leakage energy

changes

Tracking the MEP : 0.5X – 1.5X energy savings Increasing Workload 0.25 0.3 0.35 0.4 0.45 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

2-taps 5-taps 10-taps 12-taps

VDD (V) Eop (Normalized)

Temperature, Duration of Leakage

ELEAKAGE

VMEP

EACTIVE

Workload, Activity

VMEP

Operation of the Energy Minimizing Loop Operation of the Energy Minimizing Loop Operation of the Energy Minimizing Loop Operation of the Energy Minimizing Loop

VDD

Loop Start Loop Stop VDD starts at 420mV VDD settles at 370mV

370mV 320mV

VDD

Loop Start Loop Stop VDD starts at 420mV VDD settles at 370mV

370mV 320mV

• Y. Ramadass
• Y. Ramadass

Parallelism Parallelism Parallelism Parallelism

Correlator Bank Demodulation

Correlator Sub-bank 1

Correlator 1 Correlator 2 Correlator L

Correlator Sub-bank 2

Retiming Block

5 Tap FIR Filter 5 Tap FIR Filter 5 Tap FIR Filter 5 Tap FIR Filter

… … …

………

Correlator L+1 Correlator L+2 Correlator 2L

Correlator Sub-bank M

Correlator (M-1)L+1 Correlator (M-1)L+2 Correlator ML

5-bit Input from ADC Serial to Parallel Threshold Detector/ Position Encoder Bit Decoder

… … … … … … … … … Demodulated Bits

Acquisition/ Timing Control

FIR Coefficients

L = 20 M = 31 Total # of correlators = 620

• V. Sze
• V. Sze

Reduce Voltage Slower Operation Parallel banks Recover Performance Low power, with good performance (best of both worlds)

400mV 100Mbps baseband processor

Outline Outline Outline Outline

Introduction Voltage Scaling techniques Challenges with Low voltage operation System Examples Conclusion

A Typical System A Typical System A Typical System A Typical System

DSP DMA Accelerators Power Supplies Data Memory

Instruction Cache

Extreme Voltage Scaling: Sub-threshold Operation Standby Power Reduction

• Fine-grained power down
• Standby voltage scaling

Sensor(s) Radio

Sub-VT Memory Modeling and Theory

th DD

nV V DD g DP eff DD eff Total

e V KC L W V C E

−

+ =

2 2

Ultra-Dynamic Voltage Scaling

Challenges w ith sub Challenges w ith sub Challenges w ith sub Challenges w ith sub-

• threshold logic

threshold logic threshold logic threshold logic

Weak Weak

20 40 60 80 100 120 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 time (ns)

Ratioed FF Non-ratioed FF Weak Weak Strong Strong N1 N2 N3 N1 N2 N3 N1 N2 N3 N3, non- ratioed CK CK CK CK CK D Q D Q Ratioed FF fails to write a 1 at strong N, weak P corner at 400mV

Performance Order of Magnitude Higher Variability in Sub Order of Magnitude Higher Variability in Sub-

• V

VT

T

Global Local

Functionality

Local VT variation → large spread in voltage swing, delay, energy Errors due to degraded noise margins and timing violations Variation-tolerant circuits (e.g. asynchronous logic, soft error correction)

Challenges w ith sub Challenges w ith sub Challenges w ith sub Challenges w ith sub-

• threshold logic

threshold logic threshold logic threshold logic

J.Kw ong J.Kw ong

A 180mV FFT Processor A 180mV FFT Processor A 180mV FFT Processor A 180mV FFT Processor

FFT – Fast Fourier Transform Operates down to 180mV!!! 5X savings in energy at the

minimum energy point

• A. Wang
• A. Wang

SRAM Challenges SRAM Challenges SRAM Challenges SRAM Challenges

WL BL BLB WL

Static Noise Margin (SNM) degraded by variation: Cannot hold data during read!! Feedback too strong: Cannot write new data!! Bitline leakage impacts read value: Cannot read correctly!!

Lowest previous demonstrated SRAM in 65nm is 0.7V

Problem #1 Problem 2 Problem 3

Sub Sub Sub Sub-

• threshold SRAM design

threshold SRAM design threshold SRAM design threshold SRAM design

• N. Verma
• N. Verma

8-transistor SRAM cell Operates down to 350mV!!! 20X leakage power savings

Outline Outline Outline Outline

Introduction Voltage Scaling techniques Challenges with Low voltage operation System Examples Conclusion

Wireless Sensor Netw orks Wireless Sensor Netw orks Wireless Sensor Netw orks Wireless Sensor Netw orks

ADC ADC Scalable rate (0-100KS/s) and precision (12b & 8b) 25mW at 100kS/s

ADC DSP RF

Low -Ra Rate te RF RF On-Off Keying using a rectification based receiver Rx Energy: 1-3 nJ/bit [N. Verma] [D. Daly] Se Sens nsor

• r D

DSP 16-bit DSP with FFT (128-1024 points) 10pJ/instuction [D. Finchelstein

• D. Finchelstein

and N. Ickes and N. Ickes ] ADC ADC Scalable rate (0-100KS/s) and precision (12b & 8b) 25mW at 100kS/s

ADC DSP RF

Low -Ra Rate te RF RF On-Off Keying using a rectification based receiver Rx Energy: 1-3 nJ/bit [N. Verma] [D. Daly] Se Sens nsor

• r D

DSP 16-bit DSP with FFT (128-1024 points) 10pJ/instuction [D. Finchelstein

• D. Finchelstein

and N. Ickes and N. Ickes ]

Wireless Sensor Netw orks Wireless Sensor Netw orks Wireless Sensor Netw orks Wireless Sensor Netw orks

AD ADC Scalable rate (0-100KS/s) and precision (12b & 8b) 25mW at 100kS/s

ADC DSP RF

Low -Rate RF Low -Rate RF On-Off Keying using a rectification based receiver Rx Energy: 1-3 nJ/bit [N. Verma] [D. Daly] Sen Sensor DS

• r DSP

16-bit DSP with FFT (128-1024 points) 10pJ/instuction [D. Finchelstein

• D. Finchelstein

and N. Ickes and N. Ickes ] AD ADC Scalable rate (0-100KS/s) and precision (12b & 8b) 25mW at 100kS/s

ADC DSP RF

Low -Rate RF Low -Rate RF On-Off Keying using a rectification based receiver Rx Energy: 1-3 nJ/bit [N. Verma] [D. Daly] Sen Sensor DS

• r DSP

16-bit DSP with FFT (128-1024 points) 10pJ/instuction [D. Finchelstein

• D. Finchelstein

and N. Ickes and N. Ickes ]

Ultra Ultra Ultra Ultra -

• w ideband (UWB) Radio

w ideband (UWB) Radio w ideband (UWB) Radio w ideband (UWB) Radio

distance

1m 10m 100m 500Mb 50Mb 5Mb 500kb WLAN Wireless USB & Multimedia Locationing/Tagging

Advantages of UWB communications include

High Data Rate Low Interference

Integrate UWB radios on battery operated devices Need an energy efficient UWB System

Narrowband Narrowband UWB UWB

Possible UWB Applications UWB versus Narrowband

freq time

Ultra Ultra Ultra Ultra -

• low

low low low -

• Pow er Low Rate UWB

Pow er Low Rate UWB Pow er Low Rate UWB Pow er Low Rate UWB

S/H S/H S/H

S/H 4:2 MUX RF Front-end Bits Out Bits Out RF RFin

in

Center Freq Gain Control Duty Cycle

Transmitter Receiver

Edge Combiner N Digital Calibrated Channel Selection PPM Del data PRF Clock RF RFout

• ut

Pulse-width Phase Scrambling

Transmitter uses no

static power

Duty cycled at the bit level for

power savings

• D. Wentzloff and F. Lee
• D. Wentzloff and F. Lee

Hybrid CMOS/Carbon Hybrid CMOS/Carbon Hybrid CMOS/Carbon Hybrid CMOS/Carbon Nanotube Nanotube Nanotube Nanotube Systems Systems Systems Systems

Carbon Nanotube Characterization

CNT DC Impedance Characterization Chemical Sensor System CNT Sensors CMOS Interface

Parasitics Parasitics Parasitics Parasitics

CNT RF Impedance Characterization

Carbon Nanotube – CMOS Hybrid System Design

CNT Power Transistor Design

• T. Cho, K. Lee, T. Pan (Prof. J. Kong)
• T. Cho, K. Lee, T. Pan (Prof. J. Kong)

Chip Design Flow Chip Design Flow Chip Design Flow Chip Design Flow

Specifications Design (4-5 months)

Cadence Verilog (Synopsys tools,

Astro…)

Spice

Layout (1-2 months) Long Wait…(3-6 months, Prof.

asks you to start next design)

Chip comes back

Package PCB (test board) Test

Write paper (hopefully the

chip has worked)

Sub Sub Sub Sub-

• Threshold ICs

Threshold ICs Threshold ICs Threshold ICs

Sub-VT Library Test Chip and FIR (65nm CMOS)

256kb 8-T SRAM 65nm with Redundancy 256kb SRAM Array 65nm

32kb Block

DC-DC Converter & Energy Minimizing Loop ( 65nm) Highly Parallel UWB Baseband (90nm)

• Ch. 6
• Ch. 5
• Ch. 4
• Ch. 1
• Ch. 2
• Ch. 3

500MS/s ADC For UWB Using 6-way Interleaving (65nm)

500Ms/s ADC Using 36-parallel Channels (65nm)

Switched Capacitor DC-DC Converter (0.18µm)

[ISLPED06] [ISSCC06] [ISSCC07] [ISSCC07] [ICASSP06 and ISSCC07] [VLSI Symposium 06] [PESC07]

U-DVS [90nm] Adder

[ISSCC05]

Helpful Classes Helpful Classes Helpful Classes Helpful Classes

Circuits – 6.002, 6.301, 6.374, 6.376, 6.775, 6.776, 6.334 Devices – 6.012, 6.728, 6.730, 6.774 Control Theory – 6.302, 6.331 Signal/Image Processing – 6.003, 6.341, 6.344 Communication – 6.450, 6.451

Groups at MIT Groups at MIT Groups at MIT Groups at MIT

Circuit Design

• Prof. Anantha Chandrakasan
• Prof. Joel Dawson
• Prof. Hae-Seung Lee
• Prof. David Perreault
• Prof. Michael Perrott
• Prof. Rahul Sarpeshkar
• Prof. Charles Sodini
• Prof. Vladimir Stojanovic

A Sample of Microelectronics Companies A Sample of Microelectronics Companies A Sample of Microelectronics Companies A Sample of Microelectronics Companies

Intel Texas Instruments IBM Analog Devices National Semiconductor Infineon Philips ST Microelectronics

Conclusions Conclusions Conclusions Conclusions

Low Power Operation is crucial for

continued success of portable electronics

Lots of new circuit design challenges

ahead

Energy scavenged electronics has a huge

potential

Exciting field to work on, direct relevance

to industry