Fall 2017 :: CSE 306
Introduction to
Virtual Memory
Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau)
Virtual Memory Nima Honarmand (Based on slides by Prof. Andrea - - PowerPoint PPT Presentation
Fall 2017 :: CSE 306 Introduction to Virtual Memory Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau) Fall 2017 :: CSE 306 Motivating Virtual Memory (Very) old days: Uniprogramming only one process existed at a time
Fall 2017 :: CSE 306
Introduction to
Nima Honarmand (Based on slides by Prof. Andrea Arpaci-Dusseau)
Fall 2017 :: CSE 306
User Process OS Physical Memory 2n-1 Stack Code Heap
Fall 2017 :: CSE 306
Fall 2017 :: CSE 306
its own memory range
illusion of private address space to each process?
dynamic components
Stack Code Heap 2n-1
Fall 2017 :: CSE 306
concurrently?
Fall 2017 :: CSE 306
1) Time Sharing 2) Base register 3) Base + Bound registers 4) Segmentation 5) Paging
at x86 idiosyncrasies
Fall 2017 :: CSE 306
by saving CPU registers to memory when a process isn’t running
saving memory to disk when process isn’t running
Fall 2017 :: CSE 306
processes
Fall 2017 :: CSE 306
every memory reference
CPU MMU Physical Memory
Process runs here Virtual address Physical address
Fall 2017 :: CSE 306
Two operating modes:
Fall 2017 :: CSE 306
address
base mode registers
32 bits 1 bit
mode == user?
no yes
+ base
virtual address physical address
MMU
Fall 2017 :: CSE 306
base register?
1) User Process 2) OS 3) HW
1) User Process 2) OS 3) HW
Fall 2017 :: CSE 306
Fall 2017 :: CSE 306
location)
space
Fall 2017 :: CSE 306
base mode registers
32 bits 1 bit
mode == user?
no yes
+ base
virtual address physical address
MMU
< bounds?
bounds
32 bits
yes no Exception
Fall 2017 :: CSE 306
Fall 2017 :: CSE 306
Fall 2017 :: CSE 306
contiguously in physical memory
used by process
limited parts of address space
Stack Code Heap 2n-1
Fall 2017 :: CSE 306
segments
entity in address space
read/write/execute protection bits)
Stack Code Heap 2n-1
Fall 2017 :: CSE 306
segment for every memory access
above
Mechanism used in x86
Fall 2017 :: CSE 306
pointing to the segment table stored in memory)
Segment Table mode registers
1 bit
mode == user?
no yes
seg base
virtual address (segment:offset) physical address
MMU
segment in the table?
yes no Exception
< bounds? permission
yes yes
Fall 2017 :: CSE 306
Segment Base Bounds R W 0x2000 0x6ff 1 0 1 0x0000 0x4ff 1 1 2 0x3000 0xfff 1 1 3 0x0000 0x000 0 0
Seg 0; phys-addr: 0x2000 + 0x240 = 0x2240 Seg 3: out of bounds — no translation Seg 1; phys-addr: 0x0000 + 0x108 = 0x108 Seg 2; phys-addr: 0x3000 + 0x65c = 0x365c
Fall 2017 :: CSE 306
requests more from OS (e.g., UNIX: malloc calls sbrk())
extends stack implicitly
Fall 2017 :: CSE 306
grained segmentation
segmentation
switch
complex
Fall 2017 :: CSE 306
translation is fast
context switch or errors
block