[PPT] - ! VGB VT O VSB VDB Log-Companding Advanced nUt Ut Ut I D = I PowerPoint Presentation

SLIDE 1

ISCAS Monday 29th May 2000

VLSI CMOS Low-Voltage Log-Companding Filters

Francisco Serra-Graells

Paco.Serra@cnm.es Abstract

Introduction
Principle of Operation and CMOS Generalization
Basic Building Blocks
Design Methodology
Examples
Conclusions

Centro Nacional de Microelectr´

nica-IMB, Campus UAB, 08193 Bellaterra, Spain

SLIDE 2

Introduction

1

◮ Instantaneous Companding Processing

yin Compression Non-linear SignalProcessing F F

1

Expansion xin xout yout ExternallyLinearSignalProcessing DR DR

x y

< DRy DRy

y ≡ Current x ≡ Voltage High-Frequency & Low-Voltage Applications ◮ Log-Companding law: y = F (x) = ex ◮ Previous work mainly in bipolar [1] vs MOS:

Asymmetric I/V curves
Reduced ex current dynamic range
Poor output conductance
Physical mismatching
Flicker noise

◮ Few CMOS realizations [2] [3] [4] [5]

◮ New Proposal

VeryLow-VoltageApplications Advanced MOSFETModeling inSubthreshold Log-Companding Theory

y=F(x) NewAnalog CircuitTechniques B G D S

◮ EKV model [6] in weak inversion: VS,DB > VGB−VT O n

ID = ISe

VGB−VT O nUt

e

−VSB Ut

− e

−VDB Ut

! IS = 2nβU2

t Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 3

Principle of Operation 2

◮ Basic Integrator: dyout dt . = yin τ ◮ Chain Rule as proposed by [7]: dyout dt = dyout dxout dxout dxcap dxcap dt = yout dxcap dt ◮ Product of currents as defined by [8]: yout C dxcap dt | {z } = ytunyin ytun . = C τ ◮ Multipliers the Translinear Principle [9]: youtycap = ytunyin ◮ CMOS Translinear Loops?

Mj IDj Mi IDi VGBi VSBi VSBj VGBj

CCW CW CW

X

CCW

(VGB − VSB)i = X

CW

(VGB − VSB)j

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 4

CMOS Generalization 3

◮ Cancellation of signal dependent terms: X

CCW

niUt ln IDi ISi + VT Oi + (ni − 1)VSBi | {z } = X

CW

njUt ln IDj ISj + VT Oj + (nj − 1)VSBj | {z } X

CCW

Ut ln IDi ISi + VT Oi ni + (1 − 1 ni )VGBi | {z } = X

CW

Ut ln IDj ISj + VT Oj nj + (1 − 1 nj )VGBj | {z }

◮ Gate/Source Driven (G/SD) matched pairs

GD SD NMOS PMOS

◮ No GD/SD mixing!

M4 ID4 M2 ID2 M3 ID3 M1 ID1 V1 V3 V2 V4

ID1 IS ID3 IS !n3 = ID2 IS ID4 IS !n4 Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 5

Basic Building Blocks 4

◮ Rewriting the product for systematic synthesis: C dxout dt = ytunexin−xout

Ci gmAij Vj Vi Icapi

◮ State-Space matrix description: 8 > < > : dI dt = AI + BIin Iout = CI + DIin ◮ Proposed CMOS Log-Companding functions: I = F (V ) = 8 > > > > > < > > > > > : ISe − VT O+nVref nUt e V nUt GD ISe Vref −VT O nUt e − V Ut SD

dIi dt =

N

X

j=1

AijIj +

M

X

j=1

BijIinj ⇒ Ci dVi dt = 8 > > > > > > > < > > > > > > > :

N

X

j=1

ItunAije

Vj−Vi nUt

+

M

X

j=1

ItunBije

Vinj−Vi nUt

GD

N

X

j=1

−ItunAije

Vi−Vj Ut

−

M

X

j=1

ItunBije

Vi−Vinj Ut

SD

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 6

Basic Building Blocks 5

◮ Low-Voltage Saturated CMOS cells: GD SD ItunAij(Bi) nUtCiAij(Bi) UtCiAij(Bi) Compressor

Iin

Vin

Ibias Vref

+

ORA

Vin Vref Iin Ibias

+

ORA

Aij(Bi) > 0

Ci ItunAij(Bi) Vj(in) Vi ItunAij(Bi) Vj(in) Ci

VF

Vi

Aij(Bi) < 0

Ci j j ItunAij(Bi) Vj(in) Vi j j ItunAij(Bi) Vj(in) Ci

VF

Vi

Aii

Ci ItunAii Vi Ci ItunAii Vi

Expander

j j Cj Ibias Vref Iout

+

ORA

Vout

Vref j j Cj Ibias Vout Iout

+

ORA

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 7

Basic Building Blocks 6

◮ Low-Voltage Non-Saturated CMOS cells:

◮ Same Log-Companding F as Saturated SD case, but for A and B: Ci dVi dt = N X j=1 −ItunAije Vi−Vj Ut + · · · ≡ N X j=1 j=i ItunAije Vi Ut B @e −Vi Ut − e −Vj Ut 1 C A | {z } − N X j=1 ItunAij + . . . Ituni |Aii|UtCi Aij(Bi) > 0 Aik < 0

Vj Ituni Ci VF Vi IDCi 1 SAij Vk SAik CI Vin SBi

SAij(Bi)

Aij(Bi)

Aii

IDCi

Ituni PN j=1 Aij + Bi |Aii| ◮ Signal Boundaries: Time I/Ibias

1 2

1

3 5

¢V/Ut

99% 90% 75% 50%

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 8

Basic Building Blocks 7

◮ Low-Voltage Auxiliary Circuitry: GD SD Compressor

Iin Vin Ibias Vref

Ibias

Vin Vref Iin Ibias

Ibias

Expander

j j C Ibias

j

Vout Iout Vref

Ibias

Vout Iout j j C Ibias

j

Vref

Ibias CI Vout Vin Iout Iin Vout Iin

+

Iin Vout Vin Iout CI VF M2 M3 M5 M6 M1 M4

(a) (b)

X Y W W X Y

◮ Comparison:

Saturated GD area saving
Saturated SD technology independence & relaxed matching
Non-Saturated SD idem Saturated SD & low DC errors

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 9

Design Methodology 8

◮ Matrix Procedure A0, B0 and C0 (D0 ≡ 0):

1 Normalize C0 to share comp/expanders, and Yout(DC) ≡ Y (DC): C0M−1 norm . = I 2 Achieve Y (DC) ≡ Yin(DC) keeping previous C1: C1 = MopC1 ¯ 1order = −MopA−1 1 B1¯ 1inputs 3 If ∃Mop, then use an extra dummy input: ¯ 0order = A1¯ 1order + B1¯ 1inputs + ¯ Bdummy B2 = h B1| ¯ Bdummy i ◮ Circuit reductions: GD SD Compressor-Expander

Iin

Vin

Ibias

Vout

+

ORA

Iout

+

ORA

j j Cj 1 1 1 Imax 1/K

Vin Iin

+

ORA

Vout Iout

+

ORA

j j Cj 1 1 Imax 1/K

A(B)

Ci ItunAij Vj Vi Vk

Aik Aij

1 1 ItunAij Vj Ci

VF

Vi Vk

Aik Aij

1 1 Vj Ituni Ci VF Vi IDCi 1 SAij Vk SAik C I Vin SBi

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 10

Design Methodology 9 ◮ Synthesis example: SD Saturated 2nd-Order Low-Pass A = 2 6 6 4 −2ζwo −wo wo 3 7 7 5 B = 2 6 6 4 −wo 3 7 7 5 ← C =

1
D =
Anew =

2 6 6 4 −2ζwo 2ζwo −wo 2ζ 3 7 7 5 Bnew = 2 6 6 4 wo 2ζ 3 7 7 5 Cnew =

1
Dnew =
Imax

Vin Iin

+

ORA

C2

VF

Vout=V1 Iout C1 V2 2 Ituno ³ Ituno/2³ Ituno/2³

VF

2 Ituno ³ Vin Iin

+

ORA

C2

VF

Vout=V1 C1 V2 2 Ituno ³ Ituno/2³

VF

2 Ituno ³ Imax Imax Iout

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 11

Design Examples 10

◮ Common specs:

Audio Applications (e.g. Hearing Aids)
VDDmin = 1.0V
(VT ON + |VT OP |)max = 1.25V
IF ull−Scale = 4µApp
T HD <1% at 90% Full-Scale
DR =60dB to 70dB
10pF< C <100pF
1.2µm VLSI CMOS 2M 2P

◮ Saturated SD 2nd-Order High-Pass:

100 m ¹ 1

80
60
40
20

20 Frequency[KHz] 0.1 0.01 CurrentGain[dB] 4 0.5 1 1.5 2

1.5
1
0.5

0.5 1 1.5 Time[ms] OutputCurrent[ A] ¹

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 12

Design Examples 11

◮ Saturated GD 2nd-Order Band/Low-Pass:

Iin Vin Ibias

+

ORA

Vout =

1 1

V Ituno/Q C1 C2 Iout1 Ibias Ibias Vbias

+

ORA

Ituno/Q Ituno/Q QItuno QItuno Vout =

2 2

V Ibias Ituno/Q Iin Vin Ibias

+

ORA

Vout =

1 1

V Ituno/Q C1 C2 Iout1 Ibias Vbias

+

ORA

Ituno/Q QItuno Vout =

2 2

V Imax Imax Iout2 Iout2

Frequency[KHz] Iout / [dB] Iin

40
20

0.1 1 10 100 1000 0.1 1 10 100 1000

60

Iout / [dB] Iin

40
20
60

Frequency[KHz]

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 13

Design Examples 12

◮ Non-Saturated SD 3rd-Order Low-Pass:

Iin

+

ORA

Ituno C Iout

VF

Imax Ituno C

VF

Ituno C

VF

1

Iout /Iin [dB]

Frequency[kHz]

80
60
40
20

10 100 0.1

f-3/6/9dB = 3.5kHz

1 2 3 4

2
1

1 2 Time[ms]

Iout [ A] ¹ Iin =90%Full-Scale@0.5/1/2/4kHz f-3dB = 1kHz THD < 0.2%

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 14

Conclusions 13

◮ The MOSFET is suitable for Log-Companding Filtering ◮ Different types of CMOS Basic Building Blocks exist ◮ Importance of the design methodology to optimize filter area ◮ Compatibility with very Low-Voltage applications (e.g. Hearing Aids)

Francisco Serra-Graells VLSI CMOS Low-Voltage Log-Companding Filters ISCAS 2000/05/29

SLIDE 15

Bibliography 14

References [1] D.R.Frey. Log-Domain Filtering: an Approach to Current-Mode Filtering. IEE Proceedings, 140(6):406–415, Dec 1993. [2] C.Toumazou, J.Ngarmnil, and T.S.Lande. Micropower Log-Domain Filter for Electronic Cochlea. IEE Electronics Letters, 30(22):1839–1841, Oct 1994. [3] E.I.El-Masry and J.Wu. CMOS Micropower Universal Log-Domain Biquad. IEEE Transactions on Circuits and Systems-I, 46(3):389–392, Mar 1999. [4] R.M.Fox and M.Nagarajan. Multiple Operating Points in CMOS Log-Domain Filter. IEEE Transactions on Circuits and Systems-II, 46(6):705–710, Jun 1999. [5] D.Python, M.Punzenberger, and C.Enz. A 1-V CMOS Log-Domain Integrator. In ISCAS, volume II, pages 685–688. IEEE, 1999. [6] C.C.Enz, F.Krummenacher, and E.A.Vittoz. An Analytical MOS Transistor Model Valid in All Regions. . . . Kluwer Journal of Analog IC and Signal Process., 8(1):83–114, 1995. [7] R.W.Adams. Filtering in the Log-Domain. In 63rd AES Conference, May 1979. [8] E.Seevinck. Companding Current-Mode Integrator: A New Circuit Principle for Continuous-Time Monolithic

Filters. IEE Electronics Letters, 26(24):2046–2047, 1990.