Update of full silicon tracking Weiming Yao (LBNL) Silicon Tracker - - PowerPoint PPT Presentation

update of full silicon tracking
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Update of full silicon tracking Weiming Yao (LBNL) Silicon Tracker - - PowerPoint PPT Presentation

Update of full silicon tracking Weiming Yao (LBNL) Silicon Tracker Study Meeting, Sept. 23, 2016 1/4 Introduction Chengdong and I have checked the FTD construction code seems OK (segment vs petal) After digi, the strip z or v position


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SLIDE 1

1/4

Update of full silicon tracking

Weiming Yao (LBNL)

Silicon Tracker Study Meeting, Sept. 23, 2016

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SLIDE 2

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Introduction

  • Chengdong and I have checked the FTD construction

code seems OK (segment vs petal)

  • After digi, the strip z or v position is reset to the center
  • f strip, which causes them out of boundary.
  • At the moment, the fiducial check is based on geometry
  • f module, but it depends on actual hit position.
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SLIDE 3

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Tracking Efficiencies vs eta

  • Requiring PT > 1.0 GeV and in barrel and endcap overlap

region.

  • Tracking eff improves after fixing the boundary and δ-ray

1 2 3

Events 100 200 300 400 500 600 Found Tracks MC Theta

1 2 3

Efficiency

0.85 0.9 0.95 1 1.05 1.1

(b) before

1 2 3

Events 100 200 300 400 500 600 Found Tracks MC Theta

1 2 3

Efficiency

0.85 0.9 0.95 1 1.05 1.1

(c) after

1 2 3

Events 100 200 300 400 500 600 Found Tracks MC Theta

1 2 3

Efficiency

0.85 0.9 0.95 1 1.05 1.1

(d) Without delta-ray

Figure: Efficiencies vs theta

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SLIDE 4

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To-do List

  • The full silicon tracking seems in a good shape.
  • The digi and δ-ray is next to fix.
  • Dan is starting to generate some zh events and the

results will follow.

  • Instructions can be found at

http://cepc.ihep.ac.cn/ cepc/cepc twiki/index.php/Pure Silicon Detector.

  • Given more layers of silicon, the tracking seems get

slower, about twice CPU time than CEPC V1.

  • Will start to document the studies.