UnitThree MicroprocessorInput/OutputInterfacing - - PDF document

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UnitThree

MicroprocessorInput/OutputInterfacing

• Thischapteroutlinessomeofthebasic

methodsofcommunications,bothserial and parallel,betweenhumansormachinesand themicroprocessor.

• WefirstintroducethebasicI/Ointerfaceand

discussdecoding forI/Odevices.

• Then,weprovidedetailonparallel andserial

interfacing,bothofwhichhaveavarietyof applications.

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• Explaintheoperationofthebasicinputand
• utputinterfaces.
• Decodean8*,16*,and32*bitI/Odeviceso

thattheycanbeusedatanyI/Oportaddress.

• Definehandshaking andexplainhowtouseit

withI/Odevices.

• Interfaceandprogramthe82C55

programmableparallelinterface.

• InterfaceLCDdisplays,LEDdisplays,

keyboards,ADC,DAC,andvariousother devicestothe82C55.

• Interfaceandprogramthe16550serial

communicationsinterfaceadapter.

• Interfaceandprogramthe8254

programmableintervaltimer.

• (cont.)

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• Interfaceananalog*to*digitalconverter anda

digital*to*analogconverter tothe microprocessor.

• InterfacebothDC andsteppermotors tothe

microprocessor.

• (cont.)

! " #!$%#

• I/Oinstructions(IN,INS,OUT,andOUTS)are

explained.

• Alsoisolated (directorI/OmappedI/O)and

memory*mapped I/O,thebasicinput and

• utputinterfaces,andhandshaking.
• Knowledgeofthesetopicsmakesiteasierto

understandtheconnection andoperation of theprogrammable interface components andI/Otechniques.

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"

• Onetypeofinstructiontransfersinformation

toanI/Odevice(OUT).

• Anotherreads fromanI/Odevice(IN).
• Instructionsarealsoprovidedtotransfer

stringsofdatabetweenmemoryandI/O.

– INS andOUTS,foundexceptthe8086/8088

• InstructionsthattransferdatabetweenanI/O

device andthemicroprocessor’saccumulator (AL,AX,orEAX)arecalled and .

• TheI/OaddressisstoredinregisterDXasa

16*bitaddressorinthebyte(p8)immediately followingtheopcode asan8*bitaddress.

– Intelcallsthe8*bit form(p8)a& becauseitisstoredwiththeinstruction,usually inaROM

• The16*bitaddress iscalleda

becauseitisstoredinaDX,and thenusedtoaddresstheI/Odevice.

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OtherinstructionsthatuseDXtoaddress I/OaretheINS andOUTS instructions.

• I/Oportsare8bits inwidth.

– a16*bitport isactuallytwo consecutive8*bit ports beingaddressed – a32*bitI/Oport isactuallyfour8*bitports

• WhendataaretransferredusingIN orOUT,

theI/Oaddress,( orsimplyport), appearsontheaddressbus.

• ExternalI/Ointerfacedecodestheport

numberinthesamemannerasamemory address.

– the8*bitfixedportnumber (p8)appearson addressbusconnectionsA7–A0 withbits A15–A8 equalto000000002 – connectionsaboveA15 areundefined for I/Oinstruction

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• The16*bitvariableportnumber (DX)

appearsonaddressconnectionsA15–A0.

• Thefirst256I/Oport addresses(00H–FFH)

areaccessedbybothfixedandvariableI/O instructions.

– anyI/Oaddressfrom0100HtoFFFFH isonlyaccessedbythevariableI/Oaddress

• InaPCcomputer,all16addressbusbits

aredecodedwithlocations0000H–03FFH.

– usedforI/OinsidethePContheISA ()bus

• INS andOUTS instructionsaddressanI/O

deviceusingtheDXregister.

– butdonottransferdatabetweenaccumulator andI/OdeviceasdotheIN/OUTinstructions – Instead,theytransferdata betweenmemory andtheI/Odevice

• Pentium4andCore2operatinginthe64*bit

mode havethesameI/Oinstructions.

• Thereareno64*bitI/Oinstructions inthe64*

bitmode.

– mostI/Oisstill8bits andlikelywillremainso

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'('"

• TwodifferentmethodsofinterfacingI/O:

" and(".

• InisolatedI/O,theIN,INS,OUT,andOUTS

transferdatabetweenthemicroprocessor’s accumulator ormemoryandtheI/Odevice.

• Inmemory*mappedI/O,anyinstructionthat

referencesmemorycanaccomplishthe transfer.

• ThePCdoesnotusememory*mappedI/O.
• ThemostcommonI/Otransfertechnique

usedintheIntel*basedsystem isisolatedI/O.

– isolated describeshowI/Olocationsareisolated frommemoryinaseparateI/Oaddressspace

• AddressesforisolatedI/Odevices,called

ports,areseparatefrommemory.

• Becausetheportsareseparate,theusercan

expandthememorytoitsfullsizewithout usinganyofmemoryspace forI/Odevices.

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• AdisadvantageofisolatedI/Oisthatdata

transferredbetweenI/Oandmicroprocessor mustbeaccessedbytheIN,INS,OUT,and OUTS instructions.

• Separatecontrolsignals fortheI/Ospaceare

developed(usingM/IOandW/R),which indicateanI/Oread(IORC)oranI/Owrite (RD)operation.

• ThesesignalsindicateanI/Oportaddress,

whichappearsontheaddressbus,isused toselect theI/Odevice.

%)*#(Input/Output instructions.

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$+ ThememoryandI/Omapsforthe8086/8088microprocessors.(a) IsolatedI/O.(b)Memory*mappedI/O.

– inthePC,isolatedI/O portsareusedtocontrol peripheraldevices – an8*bitportaddress is usedtoaccessdevices locatedonthesystem board,suchasthetimer andkeyboard interface – a16*bitport isusedto accessserialandparallel ports,video anddiskdrive systems

• Memory*mappedI/Odoesnotuse theIN,INS,

OUT,orOUTS instructions.

• Itusesanyinstructionthattransfersdata

betweenthemicroprocessorandmemory.

– treatedasamemorylocation inmemorymap

• Advantage isanymemorytransferinstruction

canaccesstheI/Odevice.

• Disadvantage isaportionofmemorysystem

isusedastheI/Omap.

– reducesmemoryavailable toapplications

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$+, I/OmapofapersonalcomputerillustratingmanyofthefixedI/Oareas.

• "'

– thePCusespartofI/Omap for dedicatedfunctions,asshownhere – I/Ospacebetweenports0000Hand 03FFH isnormallyreservedforthe systemandISAbus – portsat0400H–FFFFH aregenerally availableforuserapplications,main* boardfunctions,andthePCIbus – 80287coprocessoruses00F8H–00FFH, soIntelreservesI/Oports00F0H–00FFH

)

• Thebasicinputdevice isasetofthree*state

buffers.

• Thebasicoutputdevice isasetofdata

latches.

• ThetermIN referstomovingdatafrom the

I/Odeviceinto themicroprocessor and

• ThetermOUT referstomovingdataout of

themicroprocessorto theI/Odevice.

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• Three*statebuffers areusedtoconstructthe

8*bitinputportdepictedinFigure11–3.

• ExternalTTLdataareconnectedtotheinputs
• fthebuffers.

– bufferoutputsconnecttothedatabus

• Thecircuitofallowstheprocessortoreadthe

contentsoftheeightswitchesthatconnectto any8*bit sectionofthedatabuswhenthe selectsignalbecomesalogic0.

$+. Thebasicinputinterface illustratingtheconnectionofeight switches.Notethatthe74ALS244isathree*statebuffer thatcontrolsthe applicationoftheswitchdatatothedatabus.

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• WhentheINinstructionexecutes,contents
• ftheswitchescopy totheALregister.
• Thisbasicinputcircuitisnotoptionaland

mustappearanytimeinputdataare interfacedtothemicroprocessor.

• Sometimesitappearsasadiscretepartofthe

circuit,asshowninFigure11–3.

– alsobuiltintoaprogrammableI/Odevices

• Sixteen* or32*bitdata canalsobeinterfaced

butisnotnearlyascommonas8*bitdata.

• Receivesdatafromtheprocessorandusually

mustholditforsomeexternaldevice.

– latchesorflip*flops,likebuffersintheinput device,areoftenbuiltintotheI/Odevice

• Fig11–4showshoweight light*emitting

diodes(LEDs)connecttotheprocessor throughasetofeight datalatches.

• Thelatchstoresthenumberoutputbythe

microprocessorfromthedatabussothatthe LEDscanbelit withany8*bitbinarynumber.

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$+/ Thebasicoutput interfaceconnectedtoasetof LEDdisplays.

• Latcheshold thedatabecausewhenthe

processorexecutesanOUT,dataareonly presentonthedatabusforlessthan1.0s.

– theviewerwouldneverseetheLEDsilluminate

• WhentheOUTexecutes,datafromAL,AX,
• rEAXtransfertothelatchviathedatabus.
• EachtimetheOUTexecutes,theSELsignal

activates,capturingdata tothelatch.

– dataarehelduntilthenextOUT

• Whentheoutputinstructionisexecuted,data

fromtheALregister appearontheLEDs.

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01+

• ManyI/Odevicesacceptorrelease

informationslower thanthemicroprocessor.

• AmethodofI/Ocontrolcalled1+
• r+,synchronizestheI/Odevicewith

themicroprocessor.

• Anexampleisaparallelprinterthatprintsa

fewhundredcharacterspersecond(CPS).

• Theprocessorcansenddatamuchfaster.

– awaytoslowthemicroprocessordowntomatch speedswiththeprintermustbedeveloped

• Fig11–5illustratestypicalinputandoutput

connectionsfoundonaprinter.

– datatransfersviadataconnections(D7–D0)

• ASCIIdataareplacedonD7–D0,andapulse

isthenappliedtotheSTBconnection.

– BUSY indicatestheprinterisbusy – STB isaclockpulseusedtosenddatatoprinter

• Thestrobesignal sendsorclocksthedata

intotheprintersothattheycanbeprinted.

– astheprinterreceivesdata,itplaceslogic1on theBUSY pin,indicatingitisprintingdata

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FIGURE 11-5 The DB25 connector found on computers and the Centronics 36-pin connector found on printers for the Centronics parallel printer interface.

• Thesoftwarepolls orteststheBUSY pinto

decidewhethertheprinterisbusy.

– Iftheprinter isbusy,theprocessorwaits – ifnot,thenextASCIIcharactergoestotheprinter

• Thisprocessofinterrogatingtheprinter,or

anyasynchronousdevicelikeaprinter,is calledhandshaking orpolling.

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• InputdevicesarealreadyTTL andcompatible,

andcanbeconnectedtothemicroprocessor anditsinterfacingcomponents.

– ortheyareswitch*based

• Switch*baseddevices areeitheropenor

connected;ThesearenotTTLlevels.

– TTLlevelsarealogic0(0.0V–0.8V) – oralogic1(2.0V–5.0V)

• Usingswitch*baseddevice asTTL*compatible

inputrequiresconditioningapplied.

$+2 Asingle*pole,single*throwswitchinterfacedasa TTLdevice.

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• Fig11–6showsatoggleswitch properly

connectedtofunctionasaninputdevice.

• Apull*upresistor ensureswhentheswitchis
• pen,theoutputsignalisalogic1.

– whentheswitchisclosed,itconnectsto ground,producingavalidlogic0level

• Astandardrange ofvaluesforpull*up

resistorsisbetween1KOhmand10KOhm.

• Mechanicalswitchcontactsphysicallybounce

whentheyareclosed,

– whichcancreateaproblemifaswitchisused asaclockingsignalforadigitalcircuit

• Topreventproblemswithbounces,oneofthe

circuitsshowninFig11–7canbeused.

– thefirst isaclassictextbookbounceeliminator – second isamorepracticalversionofthesame

• Thefirstversioncostsmoretoconstruct

– thesecondcostsrequiresnopull*upresistors andtwoinvertersinsteadoftwoNANDgates

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$+3 Debouncingswitchcontacts:(a)conventional debouncingand(b)practicaldebouncing.

– astheQinputfromtheswitchbecomesalogic0, itchangesthestateoftheflip*flop – ifthecontactbounces awayfromtheQinput,the flip*flopremembers,nochangeoccurs,andthus nobounce

• Outputdevicesaremorediverse thaninput

devices,butmanyareinterfacedinauniform manner.

• Beforeanoutputdevicecanbeinterfaced,we

mustunderstandvoltagesandcurrentsfrom themicroprocessororTTLinterface.

• VoltagesareTTL*compatible fromthe

microprocessoroftheinterfacingelement.

– logic0=0.0Vto0.4V – logic1=2.4Vto5.0V

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• Currentsforaprocessorandmanyinterfacing

componentsarelessthanforstandardTTL.

– Logic0=0.0to2.0mA – logic1=0.0to400HA

• Fig11–8showshowtointerfaceasimple

LEDtoamicroprocessorperipheralpin.

– atransistordriverisusedin11–8(a) – aTTLinverterisusedin11–8(b)

• TheTTLinverter(standardversion)provides

upto16mA ofcurrentatalogic0level

– morethanenoughtodriveastandardLED

$+4 InterfacinganLED:(a)usingatransistorand(b) usinganinverter.

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• TTLinputsignalhasminimumvalueof2.4V
• Dropacrossemitter*basejunctionis0.7V.
• Thedifferenceis1.7V

– thevoltagedropacrosstheresistor

• Thevalueoftheresistoris1.7V÷ 0.1mAor

17KJ.

– as17KJ isnotastandardvalue,an18KJ resistorischosen

• In11–8(a),weelectedtouseaswitching

transistorinplaceoftheTTLbuffer.

– 2N2222isagoodlow*cost,general*purpose switchingtransistorwithaminimumgainof100 – collectorcurrentis10mA;sobasecurrentwill be1/100ofcollectorcurrentof0.1mA

• Todeterminethevalueofthebasecurrent–

limitingresistor,usethe0.1mAbasecurrent andavoltagedropof1.7Vacrossthebase current–limitingresistor.

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• Supposeweneedtointerfacea12VDC1A

motortothemicroprocessor.

• WecannotuseaTTLinverter:

– 12Vsignalwouldburnouttheinverter – currentfarexceeds16mAinvertermaximum

• Wecannotusea2N2222transistor:

– maximumcurrentis250mAto500mA, dependingonthepackagestylechosen

• ThesolutionistouseaDarlington*pair,such

asaTIP120.

– costs25¢,canhandle4Acurrentwithheatsink

• Fig11–9illustratesamotorconnectedtothe

Darlington*pair withaminimumcurrentgain

• f7000 andamaximumcurrentof4A.
• Valueofthebiasresistoriscalculatedexactly

thesameastheoneusedintheLEDdriver.

• Thecurrentthroughtheresistoris1.0A÷

7000,orabout0.143mA.

• Voltagedropis0.9Vbecauseofthetwo

diodedrops(base/emitterjunctions).

• Thevalueofthebiasresistoris0.9V÷

0.143mAor6.29KJ.

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$+5 ADCmotorinterfacedtoasystembyusingaDarlington*pair.

– TheDarlington*pairmustuse aheatsink becauseofthe amountofcurrent – thediode mustbepresentto prevent theDarlington*pair frombeingdestroyedby inductivekickback

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• Verysimilar tomemoryaddressdecoding,

especiallyformemory*mappedI/Odevices.

• Thedifferencebetweenmemorydecoding

andisolatedI/Odecodingisthenumberof addresspinsconnectedtothedecoder.

• Inthepersonalcomputersystem,wealways

decodeall16bitsoftheI/Oportaddress.

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