Tutorial Slides for Week 9 ENEL 353: Digital Circuits Fall 2015 - PowerPoint PPT Presentation

Tutorial Slides for Week 9 ENEL 353: Digital Circuits — Fall 2015 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 3 November, 2015

slide 2/11 ENEL 353 F15 Tutorial Slides for Week 9 Topics for today Decoders. Combinational logic timing. SR latches. Comparison of D latch with D flip-flop.

slide 3/11 ENEL 353 F15 Tutorial Slides for Week 9 Exercise 1: Decoder-based logic Suppose you have been asked to implement F = ¯ A ¯ C + BC + A ¯ B ¯ C using only a 3:8 decoder, and as many 3-input OR gates as you like. No other components are available. Draw a schematic for the circuit.

slide 4/11 ENEL 353 F15 Tutorial Slides for Week 9 Exercise 2: Timing for a NAND-based full adder Here is an implementation of a 1-bit full adder using 9 NAND2 gates. (It’s true but not obvious that it implements the adder functions correctly!) A B S C IN C OUT Suppose that for a NAND2 gate, t cd = 29 ps and t pd = 40 ps. What is the overall t cd for the circuit? What is t pd from A or B to S ? From A or B to C OUT ? From to C IN to S ? From to C IN to C OUT ?

slide 5/11 ENEL 353 F15 Tutorial Slides for Week 9 Review: NOR-based SR latch We’ve seen in a lecture that the outputs will be: R Q R S Q QN 0 0 see below 0 1 1 0 QN S 1 0 0 1 1 1 0 0 When R = S = 0, (Q , QN) will be (0 , 1) if the most recent pulse was on R, and (1 , 0) if the most recent pulse was on S. If pulses on R and S end at nearly the same time, behaviour is unpredictable.

slide 6/11 ENEL 353 F15 Tutorial Slides for Week 9 Exercise 3: NAND-based SR latch Let’s do some algebra to gate 1 complete the following S table: Q R S Q QN 0 0 QN 0 1 R 1 0 gate 2 1 1

slide 7/11 ENEL 353 F15 Tutorial Slides for Week 9 Remark: The course textbook suggests on page 112 that for an SR latch, when R = S = 1, (Q , QN) must be (0 , 0). But for the NAND-based SR latch on the previous slide, that isn’t true. It’s not worthwhile to worry much about this issue, because for normal operation of an SR latch, situations where R = S = 1 should be avoided .

slide 8/11 ENEL 353 F15 Tutorial Slides for Week 9 Exercise 4: More about SR latches Complete the timing diagram to the best of your ability. R Q Why is it that during a certain S QN interval, it’s not possible to be precise about the values of Q and QN? 1 S 0 1 R 0 1 Q 0 1 QN 0

slide 9/11 ENEL 353 F15 Tutorial Slides for Week 9 Exercise 5: D latch versus D flip-flop B (i) Write one-or-two- sentence descriptions of the D Q F behaviours of D latches and D flip-flops. (ii) If A and B are functions of time, as given below, CLK A D Q G what are F and G as functions of time? 1 A 0 1 B 0

slide 10/11 ENEL 353 F15 Tutorial Slides for Week 9 Exercise 6: Adder timing overall C IN a 15 b 15 a 14 b 14 a 2 b 2 a 1 b 1 a 0 b 0 A B C IN A B C IN A B C IN A B C IN A B C IN . . . 1-bit 1-bit 1-bit 1-bit 1-bit FA FA FA FA FA C OUT S C OUT S C OUT S C OUT S C OUT S s 15 s 14 s 2 s 1 s 0 overall C OUT Assuming the 1-bit full adder design of Exercise 2, determine the overall t pd for the above circuit. Comment on why the smallest t pd in the circuit of Exercise 2 was designed to be the delay from C IN to C OUT .

slide 11/11 ENEL 353 F15 Tutorial Slides for Week 9 Upcoming weeks Tue Nov 10: No quiz . Exercises for circuits involving D flip-flops. Tue Nov 17: Quiz #4—topics to be announced closer to the date of the quiz.