SLIDE 1
Tutorial Slides for Week 9
ENEL 353: Digital Circuits — Fall 2015 Term Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Tutorial Slides for Week 9 ENEL 353: Digital Circuits Fall 2015 - - PowerPoint PPT Presentation
Tutorial Slides for Week 9 ENEL 353: Digital Circuits Fall 2015 - - PowerPoint PPT Presentation
Tutorial Slides for Week 9 ENEL 353: Digital Circuits Fall 2015 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 3 November, 2015 slide 2/11 ENEL 353 F15 Tutorial
SLIDE 2
SLIDE 3
ENEL 353 F15 Tutorial Slides for Week 9
slide 3/11
Exercise 1: Decoder-based logic
Suppose you have been asked to implement F = ¯ A¯ C + BC + A¯ B ¯ C using only a 3:8 decoder, and as many 3-input OR gates as you like. No other components are available. Draw a schematic for the circuit.
SLIDE 4
ENEL 353 F15 Tutorial Slides for Week 9
slide 4/11
Exercise 2: Timing for a NAND-based full adder
Here is an implementation of a 1-bit full adder using 9 NAND2
- gates. (It’s true but not obvious that it implements the adder
functions correctly!)
S COUT A B CIN
Suppose that for a NAND2 gate, tcd = 29 ps and tpd = 40 ps. What is the overall tcd for the circuit? What is tpd from A or B to S? From A or B to COUT? From to CIN to S? From to CIN to COUT?
SLIDE 5
ENEL 353 F15 Tutorial Slides for Week 9
slide 5/11
Review: NOR-based SR latch
Q R S QN We’ve seen in a lecture that the outputs will be: R S Q QN see below 1 1 1 1 1 1 When R = S = 0, (Q, QN) will be (0, 1) if the most recent pulse was on R, and (1, 0) if the most recent pulse was on S. If pulses on R and S end at nearly the same time, behaviour is unpredictable.
SLIDE 6
ENEL 353 F15 Tutorial Slides for Week 9
slide 6/11
Exercise 3: NAND-based SR latch
S R QN Q gate 1 gate 2 Let’s do some algebra to complete the following table: R S Q QN 1 1 1 1
SLIDE 7
ENEL 353 F15 Tutorial Slides for Week 9
slide 7/11
Remark: The course textbook suggests on page 112 that for an SR latch, when R = S = 1, (Q, QN) must be (0, 0). But for the NAND-based SR latch on the previous slide, that isn’t true. It’s not worthwhile to worry much about this issue, because for normal operation of an SR latch, situations where R = S = 1 should be avoided.
SLIDE 8
ENEL 353 F15 Tutorial Slides for Week 9
slide 8/11
Exercise 4: More about SR latches
Complete the timing diagram to the best of your ability. Why is it that during a certain interval, it’s not possible to be precise about the values of Q and QN? Q QN R S
1
S
1
R
1
Q
1
QN
SLIDE 9
ENEL 353 F15 Tutorial Slides for Week 9
slide 9/11
Exercise 5: D latch versus D flip-flop
(i) Write one-or-two- sentence descriptions of the behaviours of D latches and D flip-flops. (ii) If A and B are functions
- f time, as given below,
what are F and G as functions of time? D Q D Q A F G B
CLK
1
B
1
A
SLIDE 10
ENEL 353 F15 Tutorial Slides for Week 9
slide 10/11
Exercise 6: Adder timing
b15 b14 s15 s14 s2 s1 s0 b2 b1 b0 a15 a14
. . .
a0 a2 a1 1-bit FA
CIN A B S COUT
1-bit FA
CIN A B S COUT
1-bit FA
CIN A B S COUT
1-bit FA
CIN A B S COUT
1-bit FA
CIN A B S COUT
- verall COUT
- verall CIN
Assuming the 1-bit full adder design of Exercise 2, determine the overall tpd for the above circuit. Comment on why the smallest tpd in the circuit of Exercise 2 was designed to be the delay from CIN to COUT .
SLIDE 11