Tutorial Slides for Week 13 ENEL 353: Digital Circuits Fall 2014 - - PowerPoint PPT Presentation

Tutorial Slides for Week 13

ENEL 353: Digital Circuits — Fall 2014 Term Steve Norman, PhD, PEng

Electrical & Computer Engineering Schulich School of Engineering University of Calgary

2 December, 2014

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Topics for today

Timing constraints for synchronous sequential logic. FSM design problems. Implementation of combinational logic with ROM circuits.

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Exercise 1: Timing constraints, no clock skew

D27:3 D22:0 Q17:3 Q12:0 C L R1 R2 D1

8

Q2 8 CLK For registers, tsetup = 25 ps, thold = 10 ps, tpcq = 50 ps, tccq = 30 ps. Is there any possibility of a hold time violation at R2? If the desired TC is 500 ps, what constraints are there on the timing parameters of C L?

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Exercise 2: Timing constraints with clock skew

D27:3 D22:0 Q17:3 Q12:0 C L CLK1 CLK2 R1 R2 D1

8

Q2 8 For registers, tsetup = 25 ps, thold = 10 ps, tpcq = 50 ps, tccq = 30 ps. For C

L,

tpd = 350 ps, tcd = 200 ps. CLK1 and CLK2 come from the same source, with TC = 500 ps, but there may be some clock skew. What is the maximum tskew for reliable behaviour of R2? Suppose that buffers are available with tpd = 45 ps and tcd = 35 ps. How can they be used to allow the circuit to tolerate tskew = 70 ps?

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Exercise 3: A simple counter design

Produce a state transition diagram and a state transition table for a 2-bit “up/down” counter with two inputs A and B, with the following specification: A B behaviour counter is frozen 1 count up (00 → 01 → 10 → 11 → 00) 1 reset to 00 1 1 count down (00 → 11 → 10 → 01 → 00) (Assume that the DFFs you have do not have reset inputs, so reset has to be done using a bit pattern on A and B.)

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Exercise 4: A tricky counter design

Suppose a circuit for the counter from Exercise 3 is ready. Show how to use that, one more DFF, and some combinational gates to make a counter with a 2-bit output that cycles through the sequence 00, 01, 10, 11, 10, 01, 00, 01, . . .

S1 S0 CLK A B

Remark: This is an example of factored FSM design.

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Exercise 5: Using a ROM array for combinational logic

Old-school microprocessor kits used 7-segment displays to display numbers in hexadecimal format.

a g b c e f d

Let’s design a ROM circuit that takes a 4-bit unsigned integer as input, and outputs the appropriate 7-bit signal to a 7-segment display.

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Bus multiplexers

An N:1 M-bit bus multiplexer is a straightforward and very useful extension of the multiplexer circuits we have seen already in ENEL 353. Data from one of N M-bit input buses, is copied to an M-bit

• utput bus, according the value of one or more select inputs.

Here is a 2:1 2-bit example . . .

S C0 C1 B1 B0 Y1 Y0

1

Y1:0 = B1:0 if S = 0 C1:0 if S = 1

ENEL 353 F14 T02 Tutorial Slides for Week 13

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Exercise 6: A 4-input, 2-output ROM problem

Suppose you are asked to implement the following logic using a ROM array: Y1(B3, B2, B1, B0) = Σ(m0, m3, m4, m7, m10, m12, m15) Y0(B3, B2, B1, B0) = Σ(m1, m2, m5, m12, m13, m14) What are the “natural” dimensions for the ROM array? Suppose you have only an 8 × 4 ROM array and a 2:1 2-bit bus multiplexer. Show how you can implement the given logic functions using those two circuit elements. Remark: This solution provides some hints about how memory array designers produce arrays that are “close to square,” instead of “way too deep but not very wide.”