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Tutorial Slides for Week 12
ENEL 353: Digital Circuits — Fall 2015 Term Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Tutorial Slides for Week 12 ENEL 353: Digital Circuits Fall 2015 - - PowerPoint PPT Presentation
Tutorial Slides for Week 12 ENEL 353: Digital Circuits Fall 2015 - - PowerPoint PPT Presentation
Tutorial Slides for Week 12 ENEL 353: Digital Circuits Fall 2015 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 24 November, 2015 slide 2/9 ENEL 353 F15 Tutorial
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ENEL 353 F15 Tutorial Slides for Week 12
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Exercise 1: Mealy FSM design
Here’s a specification for an FSM:
◮ inputs are CLK, reset, and a 1-bit signal called A; ◮ output is a 1-bit signal called Y; ◮ on reset, Y should go to 0 as quickly as possible; ◮ Y should be 1 if the current value of A matches the value
- f A at the last two rising edges of CLK.
Why does this require a Mealy FSM? (Why can’t it be Moore?) Let’s draw a state transition diagram. Let’s make a combined state transition and output table, using symbols (S0, S1, etc.) to represent the states.
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For convenience, here’s a repeat of the specification:
◮ inputs are CLK, reset, and a 1-bit signal called A; ◮ output is a 1-bit signal called Y; ◮ on reset, Y should go to 0 as quickly as possible; ◮ Y should be 1 if the current value of A matches the value
- f A at the last two rising edges of CLK.
We won’t continue all the way to next-state equations and a schematic, but let’s think about some of the steps. What is the minimum number of state bits? If we choose a state encoding with that number of bits, how many rows will the truth table for next-state and output logic have? Should the state register have synchronous or asynchronous reset?
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ENEL 353 F15 Tutorial Slides for Week 12
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Exercise 2: Analysis of an FSM
r A reset
CLK
S0 S1 Y
Is this a Moore FSM or a Mealy FSM? Let’s draw a state transition diagram for the circuit.
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Exercise 3: FSM analysis, continued
Describe in English what the circuit of Exercise 2 does. Add a timing diagram if that helps with the description. (This is too fuzzy a question to put on a quiz or exam, but it’s useful to think about.)
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Exercise 4: Derivation of timing constraints
C L CLK R2 R1 Q1 D1 Q2 D2
The math for this is very easy. The hard part is remembering what the problem specifications are! If you practice the derivations a few times, it may help you remember. Let’s assume that the input to R1 is well-behaved, that R1 and R2 have the same values for timing parameters, and that there is no clock skew. Let’s derive inequalities that, when true, guarantee that setup-and-hold-time violations cannot happen at the input to R2.
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ENEL 353 F15 Tutorial Slides for Week 12
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Exercise 5: Application of timing constraints
Foo Bar Quux Zork
R1
Y Z
CLK
R2
Foo, Bar, Quux, and Zork are all combinational logic with these values for tpd, in ps: 250 for Foo, 60 for Bar, 100 for Quux, and 180 for Zork. For both R1 and R2, tsetup = 75 ps and tpcq = 33 ps. What is the minimum clock period for safe operation of the circuit? (Assume that there is no clock skew.)
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The last two tutorial periods
Tue Dec 1: Quiz #5.
◮ Topics will definitely include FSM design and analysis,
and timing of synchronous circuits with and without clock skew.
◮ It’s possible that there may also be a simple problem on