Towards an Efficient Switch Architecture for High-Radix Switches G. - PowerPoint PPT Presentation

Motivation PCIQ Switch Architecture Summary Towards an Efficient Switch Architecture for High-Radix Switches G. Mora 1 J. Flich 1 J. Duato 1 . López 1 E. Baydal 1 P O. Lysne 2 1 Department of Computer Engineering Technical University of Valencia, Spain 2 Simula Lab Oslo, Norway ACM/IEEE Symposium on Architectures for Networking and Communications Systems 2006 G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Outline Motivation 1 PCIQ Switch Architecture 2 Description Evaluation Enhancements and Cost Analysis Summary 3 G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Motivation HPC requires efficient Interconnection Networks. The Interconnection Network efficiency largely depends on the Switch design. How to build those Switches? G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Motivation HPC requires efficient Interconnection Networks. The Interconnection Network efficiency largely depends on the Switch design. How to build those Switches? G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Motivation HPC requires efficient Interconnection Networks. The Interconnection Network efficiency largely depends on the Switch design. How to build those Switches? G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Motivation HPC requires efficient Interconnection Networks. The Interconnection Network efficiency largely depends on the Switch design. How to build those Switches? Specially, how to use the pin bandwidth of such Switches? Low-radix switches with wide channels. High-radix switches with narrow channels. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Motivation HPC requires efficient Interconnection Networks. The Interconnection Network efficiency largely depends on the Switch design. How to build those Switches? Specially, how to use the pin bandwidth of such Switches? Low-radix switches with wide channels. High-radix switches with narrow channels. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Solutions to build large networks Networks Using Low-Radix Switches with Wide Channels ↑ Network Latency ↑ Network Cost ↑ Power Consumption Networks using High-Radix Switches with Narrow Channels ↓ Network Latency ↓ Network Cost ↓ Power Consumption G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Cost of Building a Switch We need to keep a high switch efficiency with an affordable cost. The cost depends on: Memory resources. Arbiter logic. Internal connection logic. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Cost of Building a Switch We need to keep a high switch efficiency with an affordable cost. The cost depends on: Memory resources. Arbiter logic. Internal connection logic. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Head of Line Blocking It largely affects the switch efficiency. It appears when a packet at the head of a queue is blocked and packets behind requesting free output ports. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Head of Line Blocking It largely affects the switch efficiency. It appears when a packet at the head of a queue is blocked and packets behind requesting free output ports. HOL! G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations OQ - Output Queueing Output Queueing - N × N Switch Memory requirements ∼ N XBar No HOL Speedup of N G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations IQ - Input Queueing Input Queued N × N Switch Memory requirements ∼ N XBar No Speedup HOL limits max. througput at 58 % G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations IQ - Input Queueing with VOQ Input Queued N × N Switch with VOQ No HOL at switch level XBar No Speedup Memory requirements ∼ N 2 G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations CIOQ - Combined Input-Output Queueing Combined Input-Output Queued N × N Switch Memory requirements ∼ 2 N XBar HOL at switch level Max. Speedup of 2 or 3 G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations BC - Buffered Crossbar Buffered Crossbar N × N Switch No HOL Low cost arbiters Memory requirements ∼ N 2 G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations HC - Hierarchical Crossbar p − Hierarchical Crossbar N × N Switch It is an intermediate solution between CIOQ and BC. A Buffered Crossbar (with N CIOQ ports) is subtituted by smaller switches (with p ports). Memory requirements ∼ N 2 p Speedup G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations None of these architectures scale (because high-cost or low switch efficiency). We need a better proposal for high-radix switches! A proposal that scales, that achieves high switch efficiency, and that eliminates HOL blocking problem. PCIQ fulfills all these requirements. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation PCIQ Switch Architecture Summary Switch Organizations None of these architectures scale (because high-cost or low switch efficiency). We need a better proposal for high-radix switches! A proposal that scales, that achieves high switch efficiency, and that eliminates HOL blocking problem. PCIQ fulfills all these requirements. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation Description PCIQ Switch Architecture Evaluation Summary Enhancements and Cost Analysis Outline Motivation 1 PCIQ Switch Architecture 2 Description Evaluation Enhancements and Cost Analysis Summary 3 G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation Description PCIQ Switch Architecture Evaluation Summary Enhancements and Cost Analysis Starting Point To be aware of the implementation cost we will present the PCIQ in a constructive way. We will monitor aspects such as Switch Efficiency, Memory Requirements and Crossbar Complexity. We start with CIOQ switch organization without speedup. Input links Output links Crossbar Input Output memory memory Routing & arbitration unit G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches

Motivation Description PCIQ Switch Architecture Evaluation Summary Enhancements and Cost Analysis First Modification: Increasing Read Bandwidth CIOQ Input links Output links Crossbar Input Output memory memory Routing & arbitration unit Switch Efficiency Memory Requeriments Crossbar Complexity In order to increase the switch efficiency, let’s increase the read bandwith of input memories. G. Mora, J. Flich, J. Duato, P . López, E. Baydal, O. Lysne Towards an Efficient Switch Architecture for High-Radix Switches