THE MULTI TI-DATAFLOW TAFLOW COMPOSE OSER R TOOL: L: A RUNTIME - - PowerPoint PPT Presentation

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Confer erence ence on Design gn and Architect ectur ures es for Signal and Image e Processing ng -2011 Electron onic ic Chips & S Systems design gn Initiat iativ ive Nov ovem ember 2nd-4th, , 2011, Tampere, e, Finland nd

slide-1
SLIDE 1

Confer erence ence on Design gn and Architect ectur ures es for Signal and Image e Processing ng -2011 Nov

  • vem

ember 2nd-4th, , 2011, Tampere, e, Finland nd Electron

  • nic

ic Chips & S Systems design gn Initiat iativ ive

THE MULTI TI-DATAFLOW TAFLOW COMPOSE OSER R TOOL: L: A RUNTIME TIME RECONFIG ONFIGUR URABLE ABLE HDL PLATFORM TFORM COMPOSE OSER

Francesca Palumbo, Nicola Carta and Luigi Raffo EOLA LAB - Microelect

  • electronic
  • nics Lab

DIEE EE - Dept. . of Electr tric ical al and Electr tron

  • nic

ic Eng. Univ ivers ersit ity of Cagliari iari - ITALY

slide-2
SLIDE 2

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation
  • Background
  • Goals
slide-3
SLIDE 3

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
slide-4
SLIDE 4

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
  • Performance assessment
  • Use-case scenario
  • Results
slide-5
SLIDE 5

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
  • Performance assessment
  • Use-case scenario
  • Results
  • Future research directions and conclusions
  • RVC extension
  • Applicable research hot topics
  • Final remarks
slide-6
SLIDE 6

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation,
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
  • Performance assessment
  • Use-case scenario
  • Results
  • Future research directions and conclusions
  • RVC extension
  • Applicable research hot topics
  • Final remarks
slide-7
SLIDE 7

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Scenar ario

  • and Problem Statemen

ent

  • Systems and applications on the market are becoming

every day more complex

  • mplex. We will be called to face the “th

the disa disapp ppearing earing computer” ph phenome enomenon non [Streit2005] [i.e. implicit interfaces, users could be un aware].

ICT TRENDS

  • Ubiquit

itous us access

  • Personal

nalize ized services

  • Delocal

alize ized computin ing and stor

  • rage

age

  • Massiv

ive e data a processing ing systems ems

  • High-qual

ualit ity virtual al reality

  • Intel

ellige ligent nt sensin ing

  • High-perfor
  • rmanc

ance real-tim ime embedd edded ed computing ng EXAMPLES

  • Domest

estic robot

  • t
  • Telepresence
  • The car of the future
  • Aerospac

ace and avionics

  • Human ++

++

  • Comput

utat atio ional nal science

  • Re

Realis listic ic games es

  • Smart camera

a netwo works

SOURCE CE: http://www.hi hipea eac.ne net/roa

  • adm

dmap

APPLICA PLICATION ION TREND NDS

slide-8
SLIDE 8

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Scenar ario

  • and Problem Statemen

ent

  • Systems and applications on the market are becoming

every day more complex

  • mplex. We will be called to face the “th

the disa disapp ppearing earing computer” ph phenome enomenon non [Streit2005] [i.e. implicit interfaces, users could be un aware].

SOURCE CE: http://www.hi hipea eac.ne net/roa

  • adm

dmap

APPLICA PLICATION ION TREND NDS

INTEGRA RATION ION, , SPECIALIZA LIZATION ION and HIGH PERFORMAN ANCE E REQUIREMENTS NTS in such COMPLEX EX COMPUTATIONA IONAL L HUNGRY ENVIRO RONM NMEN ENTS threat aten en TRADITIONA IONAL L DESIGN FLOW.

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SLIDE 9

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

STEP1: P1: Reconfi nfigur gurable able Paradigm digm

  • Systems are required to be flexible

ble and efficien ient.

  • Reconfigurable Paradigm (RP) to hw design: specialized

computing platforms, capable of changing configuration to serve the targeted computations.

ASIC GPP DSP

RP

Perform rmance ce Flexibi bility ty

slide-10
SLIDE 10

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

STEP1: P1: Reconfi nfigur gurable able Paradigm digm

  • Systems are required to be flexible

ble and efficien ient.

  • Reconfigurable Paradigm (RP) to hw design: specialized

computing platforms, capable of changing configuration to serve the targeted computations.

FINE NE- GRAINE NED COAR ARSE SE- GRAINE NED Bit-level Word-level Flexibility   Reconf. Speed   Config. Storage  

ASIC GPP DSP

RP

Perform rmance ce Flexibi bility ty

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SLIDE 11

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

STEP1: P1: Reconfi nfigur gurable able Paradigm digm

  • Systems are required to be flexible

ble and efficien ient.

  • Reconfigurable Paradigm (RP) to hw design: specialized

computing platforms, capable of changing configuration to serve the targeted computations.

FINE NE- GRAINE NED COAR ARSE SE- GRAINE NED Bit-level Word-level Flexibility   Reconf. Speed   Config. Storage  

ASIC GPP DSP

RP

Perform rmance ce Flexibi bility ty

HW HW-SW W GAP: : The e more the hw is specia cialized ized the more is diffic icult ult to program m it.

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SLIDE 12

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

STEP P 2: RVC Standard ard

  • The MPEG group has addressed the problem of defining an

efficient formalism for codecs specification: the Reconfigurable Video Coding (RVC) framework is part of the MPEG standard since may 2010.

  • Exploiting the Dataflow Model of Computation (D-MoC),

specifications are provided in the form of dataflow programs: networks of Functional Units (FUs) belonging to a standard Video Tool Library (VTL).

Decoder der Compos

  • sition
  • n

Mecha hanism

VTL (RVC VC-CAL AL FUs)

Selec ection

  • n of FUs

and Paramet eter er Assignmen ent

Abstra tract ct Decoder Model (FNL+RVC-CAL AL) Decoder r Descript ption (FNL+BSD SDL)

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SLIDE 13

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Goals s and Research ch Evoluti tion

RV RVC modular arity y can be coupled d with a coarse-gr grai ained ed RP map on a uniqu que hw substrate e multiple le D-MoC models. s.

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SLIDE 14

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

  • High-level dataflow combination tool, front-end
  • f the actual MDC tool. [DASIP 2010]

Goals s and Research ch Evoluti tion

RV RVC modular arity y can be coupled d with a coarse-gr grai ained ed RP map on a uniqu que hw substrate e multiple le D-MoC models. s.

slide-15
SLIDE 15

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

  • High-level dataflow combination tool, front-end
  • f the actual MDC tool. [DASIP 2010]
  • Multi-Dataflow Composer (MDC) tool: concrete

definition of the hardware template and of the D-MoC based mapping strategy. [DASIP 2011]

Goals s and Research ch Evoluti tion

RV RVC modular arity y can be coupled d with a coarse-gr grai ained ed RP map on a uniqu que hw substrate e multiple le D-MoC models. s.

slide-16
SLIDE 16

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

  • High-level dataflow combination tool, front-end
  • f the actual MDC tool. [DASIP 2010]
  • Multi-Dataflow Composer (MDC) tool: concrete

definition of the hardware template and of the D-MoC based mapping strategy. [DASIP 2011]

  • Integration
  • f

the full high-level to hw composition and generation framework.

Goals s and Research ch Evoluti tion

RV RVC modular arity y can be coupled d with a coarse-gr grai ained ed RP map on a uniqu que hw substrate e multiple le D-MoC models. s.

slide-17
SLIDE 17

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation,
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
  • Performance assessment
  • Use-case scenario
  • Results
  • Future research directions and conclusions
  • RVC extension
  • Applicable research hot topics
  • Final remarks
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SLIDE 18

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

D-MoC

  • C and Coarse-Gr

Grai aine ned d RP

[SOURCE: http://or

  • rcc.sour
  • urcef

efor

  • rge.

e.ne net/]

D-MoC-bas ased Formalis lism HW HW Platfor

  • rm

1:1

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SLIDE 19

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

D-MoC

  • C and Coarse-Gr

Grai aine ned d RP

[SOURCE: http://or

  • rcc.sour
  • urcef

efor

  • rge.

e.ne net/]

D-MoC-bas ased Formalis lism HW HW Platfor

  • rm

Coarse e Grained ed Re Reconfig figurab able e HW Platfor

  • rm

D-MoC-bas ased ed Formalis lism

1:1 2:1

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SLIDE 20

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Parallel and Serial MPEG-4 4 SP

  • F. Palumbo et.al. ,“RVC: A multi-dec

decoder der CAL composer

  • ser tool”, in Proc. DASIP 2010]
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SLIDE 21

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Parallel and Serial MPEG-4 4 SP

COMPLEX, EX, ERRO ROR PRO RONE AND TIME CONSUMING NG:

  • PLATFORM COMPOSITIO

ION

  • RECONFIGU

IGURATIO ION N MANAGEMENT

  • F. Palumbo et.al. ,“RVC: A multi-dec

decoder der CAL composer

  • ser tool”, in Proc. DASIP 2010]
slide-22
SLIDE 22

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Multi ti-Datafl Dataflow

  • w Composer

ser Tool

  • The Multi-Dataflow Composer (MDC) tool IS

IS an automatic platform constructor, composing different Functional Units (FUs) on a coarse-grained reconfigurable template.

  • The

MDC IS IS responsible

  • f

providing runtime programmability of the hw substrate to switch among given the dataflows.

  • The MDC IS

IS NOT capable of High Level Synthesis from dataflow to hw.

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SLIDE 23

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

MDC: C: Generalities alities

  • The MDC tool, recognizing the similarities among different

D-MoCs descriptions, automatically composes a unique reconfigurable multi-dataflow system:

– exploiting heterogeneous blocks, the FUs in the input networks described according D-MoC formalism, with homogeneous interfaces; – integrating the minimum FUs set to correctly accomplish the provided dataflows.

  • Reconfiguration is ensured by a couple of switching

element, named switching box (Sbox):

– inserted by the MDC tool at the crossroads among different dataflows to merge/separate the path of the processed data. – logically kept simple to provide high-speed reconfiguration (on

  • ne

cloc

  • ck cycle

le is is suffic icien ient).

slide-24
SLIDE 24

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

  • Compares the DAGs and merges

them into a unique C++ DAG;

  • With respect to (*), it stores the

information for the runtime reconfiguration, producing the configuration tables (CTs) of the Sbox IPs.

  • The MDC front-end:
  • Elaborates the input D-MoC inputs to create atomic actors (only) networks;
  • Translates the flattened networks into C++ Directed Acyclic Graphs (DAGs);

MDC: C: Front-En End

(*) [F. Palumbo et.al. ,“RVC: A multi-dec decoder

  • der CAL composer
  • ser tool”, in Proc. DASIP 2010]

(*)

slide-25
SLIDE 25

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

MDC: C: Back-End nd

  • The MDC back-end is responsible of assembling the HDL Verilog

coarse-grained reconfigurable hw, corresponding to the multi-dataflow C++ DAG produced by the MDC front-end.

  • Having originally N different networks in input, N-1 LUTs are

inserted in the final hw substrate, one for each CT created by the MDC front-end.

CONFIGURATION MANAGER

slide-26
SLIDE 26

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation,
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
  • Performance assessment
  • Use-case scenario
  • Results
  • Future research directions and conclusions
  • RVC extension
  • Applicable research hot topics
  • Final remarks
slide-27
SLIDE 27

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Design gn Under Test

slide-28
SLIDE 28

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Design gn Under Test

slide-29
SLIDE 29

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Design gn Under Test

slide-30
SLIDE 30

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Design gn Under Test

slide-31
SLIDE 31

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Design gn Under Test

slide-32
SLIDE 32

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Perfor

  • rman

ance ce Results

[UC UC1: Anti-Aliasing application, UC UC2: Zoom application, UC UC3: Anti-Aliasing and Zoom applications together]

slide-33
SLIDE 33

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Perfor

  • rman

ance ce Results

[UC UC1: Anti-Aliasing application, UC UC2: Zoom application, UC UC3: Anti-Aliasing and Zoom applications together]

Overhea rhead

slide-34
SLIDE 34

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Perfor

  • rman

ance ce Results

[UC UC1: Anti-Aliasing application, UC UC2: Zoom application, UC UC3: Anti-Aliasing and Zoom applications together]

CMO MOS 90 90 nm nm tech chnology, Synopsy sys Design Comp mpiler

slide-35
SLIDE 35

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Assess essmen ment: t: Perfor

  • rman

ance ce Results

[UC UC1: Anti-Aliasing application, UC UC2: Zoom application, UC UC3: Anti-Aliasing and Zoom applications together]

The more are the provided ded inp nputs, ts, the more could d be the actors overlap ap and thus the area saving ng. .

CMO MOS 90 90 nm nm tech chnology, Synopsy sys Design Comp mpiler

slide-36
SLIDE 36

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Outlin ine

  • Introduction:
  • Problem formulation,
  • Background
  • Goals
  • The Multi-Dataflow Composer tool
  • Performance assessment
  • Use-case scenario
  • Results
  • Future research directions and conclusions
  • RVC extension
  • Applicable research hot topics
  • Final remarks
slide-37
SLIDE 37

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

EOLAB/IN AB/INSA SA Cooperation eration: RVC Extension sion

  • The MDC tool is a N:1 platform builder. Orcc-VHDL is a 1:1

high level hardware compiler. Therefore, they can be integrated to compose a com

  • mpl

plete multi lti-pu purpose

  • se sys

systems ems generation ration and comp mposition

  • sition framewor
  • rk.
  • In the RVC domain, this integration will allow the creation
  • f multi-standard codec platforms.
slide-38
SLIDE 38

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Powe wer Manage agemen ment and Profiler iler

  • Power Management: trough the Sbox we foresee the

possibility of switching off large portion of the substrate belonging to currently unused dataflows.

  • Complexity Management: the MDC tool could be coupled

with a high level profiler to allow moving additional steps toward the hw-sw gap closure. Such a profiler operating at the graph level, combining lower level back-annotated information and higher level functional information, will be able for example to provide important directives for reconfiguration.

slide-39
SLIDE 39

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Final Remarks ks

  • The Multi-Dataflow Composer tool is intended to close the

gap between complex multi-purpose heterogeneous hw platforms and their sw programming:

– Leveraging on the combination of the Dataflow Model of Computation and the coarse-grained reconfigurable paradigm, it builds runtime reconfigurable multi-purpose systems, starting from the high level dataflow descriptions of the applications.

  • Benefits:

– Automatic derivation of complex hw platforms, with a very small users intervention. – Possibility of addressing any multi-purpose system, if described according to the RVC formalism. – Runtime reconfigurability is provided without neither hw shut-down nor suspension. – Concrete on-chip area saving.

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SLIDE 40

DASIP 2011 11 – Nov

  • vember

r 2nd-4th – Tampere, Finland

Acknowle nowledg dgem emen ents ts

The research leading to these results has received funding from: the European Community's Seventh Framework Programme (FP7/2007- 2013) under grant agreement no. 248424, MADNESS Project the Region

  • f

Sardinia, Young Researchers Grant, PO Sardegna FSE 2007-2013, L.R.7/2007 “Promotion of the scientific research and technological innovation in Sardinia” under grant agreement CRP-18324 RPCT Project

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SLIDE 41

Confer erence ence on Design gn and Architect ectur ures es for Signal and Image e Processing ng -2011 Nov

  • vem

ember 2nd-4th, , 2011, Tampere, e, Finland nd Electron

  • nic

ic Chips & S Systems design gn Initiat iativ ive Francesca Palumbo, Ph.D. francesc esca. a.pal alum umbo@d @diee ee.un unic ica. a.it it EOLAB - Microele lectron

  • nics

ics Lab

  • Dept. of Electric

ical l and Electronic nics Eng. Universit ity of Cagliari (ITALY)

THE MULTI TI-DATAFLOW TAFLOW COMPOSE OSER R TOOL: L: A RUNTIME TIME RECONFIG ONFIGUR URABLE ABLE HDL PLATFORM TFORM COMPOSE OSER