Chapter 8 Dataflow Descriptions in VHDL 1 benyamin@mehr.sharif.edu - - PowerPoint PPT Presentation

▶
chapter 8
SMART_READER_LITE
LIVE PREVIEW

Chapter 8 Dataflow Descriptions in VHDL 1 benyamin@mehr.sharif.edu - - PowerPoint PPT Presentation

Jun 11, 2023 231 likes •753 views

Chapter 8 Dataflow Descriptions in VHDL 1 benyamin@mehr.sharif.edu Dataflow Description Its between structural and behavioral descriptions Descriptions at this level specify the flow of data through the registers and busses of a

slide-1
SLIDE 1

1 benyamin@mehr.sharif.edu

Chapter 8

Dataflow Descriptions in VHDL

slide-2
SLIDE 2

2 benyamin@mehr.sharif.edu

Dataflow Description

  • Its between structural and behavioral

descriptions

  • Descriptions at this level specify the flow
  • f data through the registers and busses
  • f a system
  • Signal assignments constitute the primary

VHDL constructs for description of hardware at the dataflow level

slide-3
SLIDE 3

3 benyamin@mehr.sharif.edu

Multiplexing

ENTITY Mux8to1 IS PORT( i7,i6,i5,i4,i3,i2,i1,i0: IN std_logic; s2,s1,s0:IN std_logic; z:out std_logic ); END; ARCHITECTURE dataflow OF mux8to1 IS BEGIN WITH std_logic_vector’(s2,s1,s0) SELECT z<=i7 AFTER 5 NS WHEN “111” | “ZZZ”, i6 AFTER 5 NS WHEN “110” | “ZZ0” , i5 AFTER 5 NS WHEN “101” | “Z0Z”, i4 AFTER 3 NS WHEN “100” | “Z00”, i3 AFTER 3 NS WHEN “011” | “0ZZ”, i2 AFTER 3 NS WHEN “010” | “0Z0”, i1 AFTER 5 NS WHEN “001” | “00Z”, i0 AFTER 5 NS WHEN “000” , “X” WHEN OTHERS; END;

S2-0 I7 I6 I5 I4 Z I3 I2 I1 i0

slide-4
SLIDE 4

4 benyamin@mehr.sharif.edu

WITH-SELECT Syntax

WITH expression SELECT target<= waveform WHEN choices, waveform WHEN choices, waveform WHEN choices, … waveform WHEN OTHERS; Choices ::= choice {| choice }

slide-5
SLIDE 5

5 benyamin@mehr.sharif.edu

Decoder

ENTITY Mux8to1 IS PORT(adr: IN std_logic_vector(2 downto 0); so:IN std_logic_vector(7 downto 0) ); END; ARCHITECTURE dataflow OF mux8to1 IS BEGIN WITH adr SELECT so<=“00000001” AFTER 5 NS WHEN “000”, “00000010” AFTER 5 NS WHEN “001”, “00000100” AFTER 5 NS WHEN “010”, “00001000” AFTER 3 NS WHEN “011”, “00010000” AFTER 3 NS WHEN “100”, “00100000” AFTER 3 NS WHEN “101”, “01000000” AFTER 5 NS WHEN “110”, “10000000” AFTER 5 NS WHEN “111”, “XXXXXXXX” WHEN OTHERS; END;

so0 Adr0 so1 Adr1 so2 Adr2 s03 s04 s05 s06 s07

slide-6
SLIDE 6

6 benyamin@mehr.sharif.edu

Guarded Signal Assignment

ENTITY dff IS PORT(d,c : IN BIT; q,qb : OUT BIT); END; ARCHITECTURE assigning OF dff IS SIGNAL internal_state : BIT:=‘0’; BEGIN

internal_state<= d WHEN (c=‘1’ AND c’EVENT) ELSE internal_state;

q<=internal_state AFTER 5 NS; qb<=NOT internal_state AFTER 5 NS; END;

slide-7
SLIDE 7

7 benyamin@mehr.sharif.edu

Guarded Signal Assignment

ARCHITECTURE guarding OF dff IS SIGNAL internal_state : BIT:=‘0’; BEGIN ff:BLOCK (c=‘1’ AND c’EVENT) BEGIN q<=GUARDED d AFTER 5 NS; qb<=GUARDED NOT d AFTER 4 NS; END BLOCK ff; END;

GUARD Concurrent Statements

slide-8
SLIDE 8

8 benyamin@mehr.sharif.edu

Block Syntax

Lable:BLOCK (guard_expression) BEGIN Concurrent_statements; END BLOCK Lable; target<=GUARDED waveforms;

slide-9
SLIDE 9

9 benyamin@mehr.sharif.edu

Nested Guarded Blocks

ENTITY deff IS PORT(d,e,c:IN BIT; q,qb:OUT bit); END; ARCHITECTURE gurding OF deff IS BEGIN edge:BLOCK(c=‘1’ AND NOT c’STABLE) BEGIN gate:BLOCK (e=‘1’ AND GURAD) q<=GUARDED d AFTER 4 NS; qb<=GUARDED NOT d AFTER 4 NS; END BLOCK gate; END BLOCK edge; END;

slide-10
SLIDE 10

10 benyamin@mehr.sharif.edu

Disconnecting from Drivers

… …

Driving Value GUARD RHS Activation

slide-11
SLIDE 11

11 benyamin@mehr.sharif.edu

Pass Transistor Model

bi:BLOCK(si=‘1’ OR si=‘Z’) BEGIN t<=GUARDED ii; END BLOCK;

t ii si

slide-12
SLIDE 12

12 benyamin@mehr.sharif.edu

Resolving Between Several Driving Values

ARCHITECTURE x OF y IS

Signal Z: bit;

BEGIN z<=a; z<=b; z<=c; z<=d; END;

slide-13
SLIDE 13

13 benyamin@mehr.sharif.edu

Resolution Function

SIGNAL z : anding BIT; …

FUNCTION adding(drivers: BIT_VECTOR) RETURN BIT IS

VARIABLE ac:BIT:=‘1’; BEGIN FOR I IN drivers’RANGE LOOP ac:=ac AND driver(i); END LOOP; RETURN ac; END anding;

slide-14
SLIDE 14

14 benyamin@mehr.sharif.edu

Resolution Function

… … … … … …

Resolution Function

slide-15
SLIDE 15

15 benyamin@mehr.sharif.edu

Guarded Signal Assignments into Resolved Signals

A<=GUARDED z; A<=GUARDED y; … …

GUARD RHS Activation

… …

GUARD RHS Activation Resolution Function

slide-16
SLIDE 16

16 benyamin@mehr.sharif.edu

Resolved Type Declaration

SUBTYPE resolved_type IS resolution_function base_type; SUBTYPE anded_bit IS anding BIT; SUBTYPE ored_qit IS oring qit;

TYPE ored_qit_vector IS ARRAY (NATURAL RANGE<>) OF ored_qit;

SIGNAL a: anded_bit :=‘0’; SIGNAL a: anding BIT; SIGNAL t : ored_qit_vector(7 downto 0);

slide-17
SLIDE 17

17 benyamin@mehr.sharif.edu

Guarded Signals

SIGNAL ids: type kind; Kind ::= BUS|REGISTER; SIGNAL a: ored_qit REGISTER; SIGNAL b: ored_qit BUS;

slide-18
SLIDE 18

18 benyamin@mehr.sharif.edu

Guarded Signals and Resolution Function

v0 vn f(v) v0 vn f(v) v0 vn f(v) v0 vn f(null) v0 vn f is not called v0 vn Before Last Disconnection After Last Disconnection REGISTER BUS BUS REGISTER f is called with NULL range f is called with before disconnection drivers

slide-19
SLIDE 19

19 benyamin@mehr.sharif.edu

Delaying Disconnection

DISCONNECT signal_name : type after_clause; DISCONNECT ALL : type after_clause; DISCONNECT OTHERS: type after_clause;

ARCHITECTURE x OF y IS SIGNAL t,y,x,z:wired_qit; DISCONNECT t : wired_qit AFTER 4 NS; DISCONNECT OTHERS : wired_qit AFTER 5 NS;

  • -DISCONNECT ALL : wired_qit AFTER 6 NS;

BEGIN … END;

slide-20
SLIDE 20

20 benyamin@mehr.sharif.edu

Guarded Signal and Resolution Function

… …

z

guard_exp

RHS Activation x

BLOCK(guard_exp) BEGIN z<=GUARDED x; END BLOCK;

Resolution Function

slide-21
SLIDE 21

21 benyamin@mehr.sharif.edu

Resolving INOUT Signals

  • An implicit IN port and an implicit OUT port

exist for each INOUT line

Entity 2 Entity 1 x y x y

slide-22
SLIDE 22

22 benyamin@mehr.sharif.edu

Dataflow State Machine Description

  • Mealy machine: output is a function of the

input while the machine is in a stable state

  • Moore machine: output is a function of the

machine state

slide-23
SLIDE 23

23 benyamin@mehr.sharif.edu

Mealy 1011 Sequence Detector

101 1 10 0/0 1/0 1/1 0/0 1/0 0/0 0/0 1/0

slide-24
SLIDE 24

24 benyamin@mehr.sharif.edu

Mealy 1011 Sequence Detector

Entity Detector IS PORT(x,clk: IN BIT; z: OUT BIT); END; ARCHITECTURE singular_state OF detector IS TYPE state IS (reset,got1,got10,got101); TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state; FUCNTION one_of(sources:state_vector) RETURN state IS BEGIN RETURN sources(soures’LEFT); END; SIGNAL current : one_of state REGISTER :=reset; BEGIN

  • -next page

?

slide-25
SLIDE 25

25 benyamin@mehr.sharif.edu

Mealy 1011 Sequence Detector

Clocking: BLOCK (clk=‘1’ AND clk’EVENT) BEGIN s1:BLOCK(current=reset AND GUARD) current<=GAURDED got1 WHEN x=‘1’ ELSE reset; END BLOCK s1; s2:BLOCK(current=got1 AND GUARD) current<=GAURDED got10 WHEN x=‘0’ ELSE got1; END BLOCK s2; s3:BLOCK(current=got10 AND GUARD) current<=GAURDED got101 WHEN x=‘1’ ELSE reset; END BLOCK s3; s4:BLOCK(current=got101 AND GUARD) current<=GAURDED got1 WHEN x=‘1’ ELSE got10; END BLOCK s4; z<=‘1’ WHEN (current = got101 AND x=‘1’) ELSE ‘0’; END BLOCK clocking; END singular_state;

slide-26
SLIDE 26

26 benyamin@mehr.sharif.edu

Generic State Machine

ENTITY detector IS PORT(x,clk: IN Bit; z: OUT BIT); GENERIC(N:integer); END; ARCHITECTURE moore OF Detector IS FUNCTION oring(drivers:BIT_VECTOR) RETURN BIT IS VARIABLE a: BIT:=‘0’; BEGIN FOR i IN drivers’RANGE LOOP a:=a OR drivers(i); END LOOP; END; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY(NATURAL RANGE<>) OF ored_bit; TYPE next_table IS ARRAY ( 1 to n,BIT) OF INTEGER; TYPE out_table IS ARRAY ( 1 to n,BIT) OF BIT; SIGNAL o : ored_bit REGISTER; SIGNAL s: ored_bit_vector (1 TO 6) REGISTER := “100010”;

  • -next page
slide-27
SLIDE 27

27 benyamin@mehr.sharif.edu

Generic State Machine

BEGIN clocking: BLOCK(clk=‘1’ AND clk’EVENT) g: FOR i IN s’RANGE GENERATE si:BLOCK(s(i)=‘1’ AND GUARD) BEGIN s(next_val(I,’0’))<=GUARDED ‘1’ WHEN x=‘0’ ELSE ‘0’; s(next_val(I,’1’))<=GUARDED ‘1’ WHEN x=‘1’ ELSE ‘0’;

  • <=GUARDED out_val(I,x);

END BLOCK si; s(i)<=GUARDED ‘0’; END GENERATE; END BLOCK clocking; z<=o; END;

slide-28
SLIDE 28

28 benyamin@mehr.sharif.edu

Machine Description

  • - ‘0’,’1’

x=0 x=1 CONSTANT next_val : next_table := ((1,2), --s1: z= s1 s2 (1,3), --s2: z= s1 s3 (1,4), --s3: z= s1 s4 (1,1), --s4: z= s1 s1 (5,6), --s5: z= s5 s6 (5,6)); --s6: z= s5 s6

  • - ‘0’,’1’

x=0 x=1 CONSTANT out_val : out_table := ((‘0’,’0’), --s1: z= 0 0 (‘0’,’0’), --s2: z= 0 0 (‘0’,’0’), --s3: z= 0 0 (‘1’,’1’), --s4: z= 1 1 (‘0’,’0’), --s5: z= 0 0 (‘1’,’1’)); --s6: z= 1 1

slide-29
SLIDE 29

29 benyamin@mehr.sharif.edu

Open Collector Gates

ENTITY nand2 IS PORT(a,b:IN std_ulogic; z:OUT std_ulogic); END; ARCHITECTURE open_collector OF nand2 IS BEGIN z<=‘0’ AFTER 10 NS WHEN (a AND b)=‘1’ ELSE ‘Z’ AFTER 5 NS WHEN (a AND b)=‘0’ ELSE ‘X’ AFTER 7 NS; END;

slide-30
SLIDE 30

30 benyamin@mehr.sharif.edu

Pull-Up Signal

SIGNAL pull_up : anded std_ulogic;

  • Anded resolution function produces ‘1’ if

none of its drivers is ‘0’

  • Anded resolution function produces ‘0’ if one
  • f its drivers is ‘0’
slide-31
SLIDE 31

31 benyamin@mehr.sharif.edu

Three-State Bussing

Unit1 Unit2

Alu

Reg1 BUS non-resolved type non-resolved type resolved type Bus Controller Signal busa:std_logic_vector(7 downto 0):=“ZZZZZZZZ”;

slide-32
SLIDE 32

32 benyamin@mehr.sharif.edu

Chapter 9

Behavioral Description in VHDL

slide-33
SLIDE 33

33 benyamin@mehr.sharif.edu

Process Statement

  • Simple signal assignment is a process

which is always active and executing concurrently with other processes

  • Signal assignment is sensitive to signals
  • n the right-hand side
  • A process statement can assign values to

more than one signal

slide-34
SLIDE 34

34 benyamin@mehr.sharif.edu

Process Declarative Part

  • Variable
  • File
  • Constant
  • These object stay alive for entire

simulation run

slide-35
SLIDE 35

35 benyamin@mehr.sharif.edu

Process Statement Part

  • Process statement part is sequential body
  • Process statement part executes in zero simulation time or 1 internal

delta delay

  • Each sequential statement in process executes in 0 delta

delay

PROESS BEGIN . . . END PROCESS; 1 Delta Delay Repeat Forever

slide-36
SLIDE 36

36 benyamin@mehr.sharif.edu

Process Syntax

PROCESS [(sensitivity_list)] BEGIN sequential statements and signal asssignment END PROCESS;

slide-37
SLIDE 37

37 benyamin@mehr.sharif.edu

Signal Assignment in Process Statement

PROCESS BEGIN … x<=‘1’; IF x=‘1’ THEN statement1; ELSE statement2; END IF; END PROCESS;

Consumes 1 Delta Delay

slide-38
SLIDE 38

38 benyamin@mehr.sharif.edu

Sensitivity List

  • Sensitivity list is a mechanism for

suspending process execution

  • Conditionally activating process statement
  • If any event occur on signals in sensitivity

list, process will execute one times

slide-39
SLIDE 39

39 benyamin@mehr.sharif.edu

D-Flip Flop Example

ENTITY dff IS PORT(d,clk,rst,set: IN std_logic;q,qb:OUT std_logic); END; ARCHITECTURE behavioral OF dff IS BEGIN PROCESS(d,rst,set,clk) BEGIN IF rst=‘1’ THEN q<=‘0’; ELSIF set=‘1’ THEN q<=‘1’; ELSIF(clk’EVENT AND clk=‘1’) THEN q<=d after 10 ns; END IF; END PROCESS; qb<=NOT q; END;

slide-40
SLIDE 40

40 benyamin@mehr.sharif.edu

Postponed Process

  • Sensitive signals may activate process

statement more than one times in one real time because of delta delay events

  • Posponded process executes process

after all signals in sensitivity list become stable

slide-41
SLIDE 41

41 benyamin@mehr.sharif.edu

Postponed Process

Dff: POSTPONED PROCESS (rst,set,clk) Dff: PROCESS (rst,set,clk) t1+1d t1+2d t1+3d t1+4d clk set rst

slide-42
SLIDE 42

42 benyamin@mehr.sharif.edu

Passive Process

  • A process without any signal assignment

is a passive process

  • Concurrent procedure call and assertion

statement qualify as passive statement

  • Any passive statement may be used in

statement part of an entity declaration

slide-43
SLIDE 43

43 benyamin@mehr.sharif.edu

Passive Process

ENTITY x IS PORT(a,b,…); w:PROCESS(a,b) BEGIN some shared variable assignment END PROCESS; END; ARCHITECTURE passive OF x IS BEGIN z<=shared variabe; END;

slide-44
SLIDE 44

44 benyamin@mehr.sharif.edu

Process Flow Control

  • NEXT & EXIT statements can be used in

loop statements

  • NEXT statement causes the rest of the

loop skipped and next iteration to be taken

  • EXIT statement causes the termination of

the loop

NEXT loop_lable WHEN condition; EXIT WHEN cond;

slide-45
SLIDE 45

45 benyamin@mehr.sharif.edu

Assertion Statement

  • Is a useful statement for observing activity

in a circuit

  • Assertion Statement is passive process

and can be used in entity declaration part

ASSERTION cond REPORT string SEVERITY severity_level Severity_level::= NOTE | WARNING | ERROR | FAILURE

slide-46
SLIDE 46

46 benyamin@mehr.sharif.edu

Assertion Statement

ENTITY dff IS PORT(d,clk,rst,set: IN std_logic;q,qb:OUT std_logic); END; ARCHITECTURE behavioral OF dff IS BEGIN PROCESS(d,rst,set,clk) BEGIN ASSERT (NOT(set=‘1’ AND rst=‘1’)) REPORT “set and reset both are 1” SEVERITY NOTE; IF rst=‘1’ THEN q<=‘0’; ELSIF set=‘1’ THEN q<=‘1’; ELSIF(clk’EVENT AND clk=‘1’) THEN q<=d after 10 ns; END IF; END PROCESS; qb<=NOT q; END;

slide-47
SLIDE 47

47 benyamin@mehr.sharif.edu

Wait Statement

  • Is a behavioral construct for modeling

delays

  • Only can be used in process and

procedure

  • No sensitivity list must be declared with

wait statement

slide-48
SLIDE 48

48 benyamin@mehr.sharif.edu

Wait Statement

  • WAIT as delay statement

WAIT FOR waiting_time;

  • WAIT as an event detector

WAIT ON sensitivity_list;

  • WAIT as condition checker

WAIT UNTIL condition;

  • WAIT forever

WAIT;

  • WAIT exactly 1 delta delay

WAIT FOR 0 NS;

slide-49
SLIDE 49

49 benyamin@mehr.sharif.edu

Clock Generation

PROCESS BEGIN clk<=‘1’; WAIT FOR 10 NS; clk<=‘0’; WAIT FOR 15 NS; END PROCESS;

slide-50
SLIDE 50

50 benyamin@mehr.sharif.edu

Handshaking

A B data ready accept

slide-51
SLIDE 51

51 benyamin@mehr.sharif.edu

Handshaking

A:PROCES BEGIN data<=new_data; ready<=‘1’; WAIT UNTIL accept=‘1’; ready<=‘0’; END PROCESS; B:PROCES BEGIN WAIT UNTIL ready=‘1’ new_data<=data; accept<=‘1’; WAIT UNTIL ready=‘0’ accept<=‘0’; END PROCESS;