Chapter 8 Dataflow Descriptions in VHDL 1 benyamin@mehr.sharif.edu
Dataflow Description • Its between structural and behavioral descriptions • Descriptions at this level specify the flow of data through the registers and busses of a system • Signal assignments constitute the primary VHDL constructs for description of hardware at the dataflow level 2 benyamin@mehr.sharif.edu
Multiplexing ENTITY Mux8to1 IS PORT( i7,i6,i5,i4,i3,i2,i1,i0: IN std_logic; S2-0 s2,s1,s0:IN std_logic; z:out std_logic ); END; I7 ARCHITECTURE dataflow OF mux8to1 IS I6 BEGIN WITH std_logic_vector’(s2,s1,s0) SELECT I5 z<=i7 AFTER 5 NS WHEN “111” | “ZZZ”, i6 AFTER 5 NS WHEN “110” | “ZZ0” , I4 Z i5 AFTER 5 NS WHEN “101” | “Z0Z”, I3 i4 AFTER 3 NS WHEN “100” | “Z00”, i3 AFTER 3 NS WHEN “011” | “0ZZ”, I2 i2 AFTER 3 NS WHEN “010” | “0Z0”, i1 AFTER 5 NS WHEN “001” | “00Z”, I1 i0 AFTER 5 NS WHEN “000” , “X” WHEN OTHERS; i0 END; 3 benyamin@mehr.sharif.edu
WITH-SELECT Syntax WITH expression SELECT target<= waveform WHEN choices, waveform WHEN choices, waveform WHEN choices, … waveform WHEN OTHERS; Choices ::= choice {| choice } 4 benyamin@mehr.sharif.edu
Decoder ENTITY Mux8to1 IS PORT(adr: IN std_logic_vector(2 downto 0); so:IN std_logic_vector(7 downto 0) ); END; so0 ARCHITECTURE dataflow OF mux8to1 IS Adr0 so1 BEGIN WITH adr SELECT Adr1 so2 so<=“00000001” AFTER 5 NS WHEN “000”, “00000010” AFTER 5 NS WHEN “001”, Adr2 s03 “00000100” AFTER 5 NS WHEN “010”, “00001000” AFTER 3 NS WHEN “011”, s04 “00010000” AFTER 3 NS WHEN “100”, s05 “00100000” AFTER 3 NS WHEN “101”, “01000000” AFTER 5 NS WHEN “110”, s06 “10000000” AFTER 5 NS WHEN “111”, “XXXXXXXX” WHEN OTHERS; s07 END; 5 benyamin@mehr.sharif.edu
Guarded Signal Assignment ENTITY dff IS PORT(d,c : IN BIT; q,qb : OUT BIT); END; ARCHITECTURE assigning OF dff IS SIGNAL internal_state : BIT:=‘0’; BEGIN internal_state<= d WHEN (c=‘1’ AND c’EVENT) ELSE internal_state; q<=internal_state AFTER 5 NS; qb<=NOT internal_state AFTER 5 NS; END; 6 benyamin@mehr.sharif.edu
Guarded Signal Assignment ARCHITECTURE guarding OF dff IS SIGNAL internal_state : BIT:=‘0’; BEGIN GUARD ff:BLOCK (c=‘1’ AND c’EVENT) BEGIN q<=GUARDED d AFTER 5 NS; qb<=GUARDED NOT d AFTER 4 NS; END BLOCK ff; END; Concurrent Statements 7 benyamin@mehr.sharif.edu
Block Syntax Lable:BLOCK (guard_expression) BEGIN Concurrent_statements; END BLOCK Lable; target<=GUARDED waveforms; 8 benyamin@mehr.sharif.edu
Nested Guarded Blocks ENTITY deff IS PORT(d,e,c:IN BIT; q,qb:OUT bit); END; ARCHITECTURE gurding OF deff IS BEGIN edge:BLOCK(c=‘1’ AND NOT c’STABLE) BEGIN gate:BLOCK (e=‘1’ AND GURAD) q<=GUARDED d AFTER 4 NS; qb<=GUARDED NOT d AFTER 4 NS; END BLOCK gate; END BLOCK edge; END; 9 benyamin@mehr.sharif.edu
Disconnecting from Drivers RHS Activation GUARD … 0 Driving Value … 10 benyamin@mehr.sharif.edu
Pass Transistor Model ii si t bi:BLOCK(si=‘1’ OR si=‘Z’) BEGIN t<=GUARDED ii; END BLOCK; 11 benyamin@mehr.sharif.edu
Resolving Between Several Driving Values ARCHITECTURE x OF y IS Signal Z: bit; BEGIN z<=a; z<=b; z<=c; z<=d; END; 12 benyamin@mehr.sharif.edu
Resolution Function SIGNAL z : anding BIT; … FUNCTION adding(drivers: BIT_VECTOR) RETURN BIT IS VARIABLE ac:BIT:=‘1’; BEGIN FOR I IN drivers’RANGE LOOP ac:=ac AND driver(i); END LOOP; RETURN ac; END anding; 13 benyamin@mehr.sharif.edu
Resolution Function … 0 … … 0 … Resolution … 0 Function … 14 benyamin@mehr.sharif.edu
Guarded Signal Assignments into Resolved Signals RHS Activation GUARD A<=GUARDED z; … 0 A<=GUARDED y; … RHS Activation GUARD … Resolution 0 Function … 15 benyamin@mehr.sharif.edu
Resolved Type Declaration SUBTYPE resolved_type IS resolution_function base_type; SUBTYPE anded_bit IS anding BIT; SUBTYPE ored_qit IS oring qit; TYPE ored_qit_vector IS ARRAY (NATURAL RANGE<>) OF ored_qit; SIGNAL a: anded_bit :=‘0’; SIGNAL a: anding BIT; SIGNAL t : ored_qit_vector(7 downto 0); 16 benyamin@mehr.sharif.edu
Guarded Signals SIGNAL ids: type kind; Kind ::= BUS|REGISTER; SIGNAL a: ored_qit REGISTER; SIGNAL b: ored_qit BUS; 17 benyamin@mehr.sharif.edu
Guarded Signals and Resolution Function v0 v0 f(null) f is called with f(v) NULL range vn vn BUS BUS v0 v0 f(v) f is not called vn vn REGISTER REGISTER v0 v0 f is called with before f(v) disconnection drivers vn vn After Last Before Last Disconnection 18 Disconnection benyamin@mehr.sharif.edu
Delaying Disconnection DISCONNECT signal_name : type after_clause; DISCONNECT ALL : type after_clause; DISCONNECT OTHERS: type after_clause; ARCHITECTURE x OF y IS SIGNAL t,y,x,z:wired_qit; DISCONNECT t : wired_qit AFTER 4 NS; DISCONNECT OTHERS : wired_qit AFTER 5 NS; --DISCONNECT ALL : wired_qit AFTER 6 NS; BEGIN … END; 19 benyamin@mehr.sharif.edu
Guarded Signal and Resolution Function BLOCK(guard_exp) BEGIN RHS Activation z<=GUARDED x; x END BLOCK; guard_exp … 0 z … Resolution Function 20 benyamin@mehr.sharif.edu
Resolving INOUT Signals • An implicit IN port and an implicit OUT port exist for each INOUT line x y Entity 1 Entity 2 y x 21 benyamin@mehr.sharif.edu
Dataflow State Machine Description • Mealy machine: output is a function of the input while the machine is in a stable state • Moore machine: output is a function of the machine state 22 benyamin@mehr.sharif.edu
Mealy 1011 Sequence Detector 0/0 0 1/0 1/0 1/1 1 101 0/0 1/0 0/0 0/0 10 23 benyamin@mehr.sharif.edu
Mealy 1011 Sequence Detector Entity Detector IS PORT(x,clk: IN BIT; z: OUT BIT); END; ARCHITECTURE singular_state OF detector IS TYPE state IS (reset,got1,got10,got101); TYPE state_vector IS ARRAY (NATURAL RANGE <>) OF state; FUCNTION one_of(sources:state_vector) RETURN state IS BEGIN RETURN sources(soures’LEFT); ? END; SIGNAL current : one_of state REGISTER :=reset; BEGIN --next page 24 benyamin@mehr.sharif.edu
Mealy 1011 Sequence Detector Clocking: BLOCK (clk=‘1’ AND clk’EVENT) BEGIN s1:BLOCK(current=reset AND GUARD) current<=GAURDED got1 WHEN x=‘1’ ELSE reset; END BLOCK s1; s2:BLOCK(current=got1 AND GUARD) current<=GAURDED got10 WHEN x=‘0’ ELSE got1; END BLOCK s2; s3:BLOCK(current=got10 AND GUARD) current<=GAURDED got101 WHEN x=‘1’ ELSE reset; END BLOCK s3; s4:BLOCK(current=got101 AND GUARD) current<=GAURDED got1 WHEN x=‘1’ ELSE got10; END BLOCK s4; z<=‘1’ WHEN (current = got101 AND x=‘1’) ELSE ‘0’; END BLOCK clocking; END singular_state; 25 benyamin@mehr.sharif.edu
Generic State Machine ENTITY detector IS PORT(x,clk: IN Bit; z: OUT BIT); GENERIC(N:integer); END; ARCHITECTURE moore OF Detector IS FUNCTION oring(drivers:BIT_VECTOR) RETURN BIT IS VARIABLE a: BIT:=‘0’; BEGIN FOR i IN drivers’RANGE LOOP a:=a OR drivers(i); END LOOP; END; SUBTYPE ored_bit IS oring BIT; TYPE ored_bit_vector IS ARRAY(NATURAL RANGE<>) OF ored_bit; TYPE next_table IS ARRAY ( 1 to n,BIT) OF INTEGER; TYPE out_table IS ARRAY ( 1 to n,BIT) OF BIT; SIGNAL o : ored_bit REGISTER; SIGNAL s: ored_bit_vector (1 TO 6) REGISTER := “100010”; --next page 26 benyamin@mehr.sharif.edu
Generic State Machine BEGIN clocking: BLOCK(clk=‘1’ AND clk’EVENT) g: FOR i IN s’RANGE GENERATE si:BLOCK(s(i)=‘1’ AND GUARD) BEGIN s(next_val(I,’0’))<=GUARDED ‘1’ WHEN x=‘0’ ELSE ‘0’; s(next_val(I,’1’))<=GUARDED ‘1’ WHEN x=‘1’ ELSE ‘0’; o<=GUARDED out_val(I,x); END BLOCK si; s(i)<=GUARDED ‘0’; END GENERATE; END BLOCK clocking; z<=o; END; 27 benyamin@mehr.sharif.edu
Machine Description -- ‘0’,’1’ x=0 x=1 CONSTANT next_val : next_table := ((1,2), --s1: z= s1 s2 (1,3), --s2: z= s1 s3 (1,4), --s3: z= s1 s4 (1,1), --s4: z= s1 s1 (5,6), --s5: z= s5 s6 (5,6)); --s6: z= s5 s6 -- ‘0’,’1’ x=0 x=1 CONSTANT out_val : out_table := ((‘0’,’0’), --s1: z= 0 0 (‘0’,’0’), --s2: z= 0 0 (‘0’,’0’), --s3: z= 0 0 (‘1’,’1’), --s4: z= 1 1 (‘0’,’0’), --s5: z= 0 0 (‘1’,’1’)); --s6: z= 1 1 28 benyamin@mehr.sharif.edu
Open Collector Gates ENTITY nand2 IS PORT(a,b:IN std_ulogic; z:OUT std_ulogic); END; ARCHITECTURE open_collector OF nand2 IS BEGIN z<=‘0’ AFTER 10 NS WHEN (a AND b)=‘1’ ELSE ‘Z’ AFTER 5 NS WHEN (a AND b)=‘0’ ELSE ‘X’ AFTER 7 NS; END; 29 benyamin@mehr.sharif.edu
Pull-Up Signal SIGNAL pull_up : anded std_ulogic; •Anded resolution function produces ‘1’ if none of its drivers is ‘0’ •Anded resolution function produces ‘0’ if one of its drivers is ‘0’ 30 benyamin@mehr.sharif.edu
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