The CMS Inner Tracker Upgrade for the HL-LHC Malte Backhaus for the - - PowerPoint PPT Presentation

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The CMS Inner Tracker Upgrade for the HL-LHC Malte Backhaus for the - - PowerPoint PPT Presentation

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The CMS Inner Tracker Upgrade for the HL-LHC Malte Backhaus for the CMS Collaboration Malte Backhaus | PIXEL2018 | | 10/12/2018 | | 1 Motivation and requirements Experimental conditions at HL-LHC Luminosity increase by factor

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Malte Backhaus for the CMS Collaboration

The CMS Inner Tracker Upgrade for the HL-LHC

10/12/2018 Malte Backhaus | PIXEL2018 1

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Experimental conditions at HL-LHC

  • Luminosity increase by factor 7.5 to ~1035 cm-2s-1

 200 pile-up vertices  10.000 particle tracks per event

  • 25 ns bunch-crossing separation
  • Collect up to 4000 fb-1 of data

 ~10 years of operation

  • 3.8 T magnetic field

Requirements for the CMS Tracker in Phase 2

  • Provide trigger information using transverse

momentum of tracks  pT-modules in Outer Tracker  latency increase to 12.5 μs (currently 3.75 μs)  Trigger rate increase to 750 kHz

  • Occupancy of up to 3.5 GHz/cm2 in pixel layer one
  • Radiation levels up to
  • fluence of 2.3 x 1016 1 MeV neqcm-2
  • Total ionizing dose of 1.2 Grad

10/12/2018 Malte Backhaus | PIXEL2018 2

Motivation and requirements

Innermost layer: 2.3x1016 neq/cm2 Outer & Service cylinder: 1015 neq/cm2 Innermost layer: 1.2 Grad Outer & Service cylinder: 100Mrad

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CMS Phase 2 Tracker

TDR EDR

Pixel Phase 1 Installation

EDR

Pixel Phase 2 Installation

Outer Tracker: Strip-strip pt-modules Strip-pixel pt-modules Inner Tracker: 2x2 pixel modules 1x2 pixel modules

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IT overview

Tracker Extension PiXel 4 disks Dimensions

~4.9 m2 of pixel surface, 2 billion channels

Simple mechanics

no turbines-tilted modules

Simple installation/removal

for potential replacement/repair of parts

IT volume increase at z = 1600mm

installation from both sides in 8 parts

Tracker Forward PiXel 8 disks Tracker Barrel PiXel 4 layers

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IT layout

TFPX:

  • 8 disks per side
  • 4 rings per disk

TEPX:

  • 4 disks/end
  • 5 rings/disk

New proposal

2x2 and 1x2 modules TBPX TFPX TEPX

TBPX:

  • 4 layers
  • 4/5 modules per ladder
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Major challenges (focussed on in this talk)

Sensor radiation tolerance  efficiency, power consumption track density  hit occupancy (cluster size in magnetic field) Readout chip radiation tolerance  hit occupancy, trigger latency hit occupancy, trigger latency  power consumption Pixel modules low mass  power consumption, data rate removable  connection to chains, thermal management Detector system power consumption  low mass services Mechanics lightweight and removable mechanics  high thermal load

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n-in-p sensors with:

1. Radiation tolerance  thin sensors: 100-150 µm thickness: expected signal / threshold > 3 at Φeq ≈ 8x1015 cm-2 2. Track density  reduce pixel size by factor of six: 25x100 or 50x50 µm2 under study 3. High efficiency  pixel cell design: Isolation, biasing scheme, layout details

3D sensors:

  • See poster by M. Meschini

10/12/2018 Malte Backhaus | PIXEL2018 7

Sensor design and testing

Expected threshold CMS ROC

Simulation

  • J. Schwandt

25x100 μm2 (baseline) 50x50 μm2

CMS sensors bump-bonded to RD53A chips allows to test to required radiation levels: Light carrier board for irradiation campaigns (88 sensors) and tests beams in 2018-2019

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Thin n-in-p test-beam

  • RD53A Single chip assembly, in-pixel efficiency of four pixel cell shown
  • Beam at vertical incidence (as in TFPX and TEPX)

Higher efficiency with bias dot floating

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Thin n-in-p test-beam

Higher (better) charge sharing between pixels with bias dot floating

  • RD53A Single chip assembly, in-pixel cluster size map of four pixel cell shown
  • Beam at vertical incidence (as in TFPX and TEPX)
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RD53 readout chip - common design with ATLAS

RD53A chip ( ½ size of final chip) Design features:

  • 50 x 50 µm2 pixels
  • 3 Analog Front-Ends
  • 2 digital architectures
  • Shunt-LDO for serial powering
  • 4 x 1.28 Gbps output links
  • 1 x 160 Mbps control link

Technology and design concept:

  • 65nm feature size
  • Analog islands (manual layout) in a

Digital Sea (synthesized)  Intense modelling and verification prior to submission

Active test program:

  • Chip is fully functional
  • Meeting 500 Mrad tolerance specification

 Could reach 1 Grad (controlled conditions)?

  • All Analog Front-Ends show good performance with radiation
  • Low Threshold < 1000e-

Working intensively on RD53B design CMS final chip submission: End of 2019

RD53A functional floorplan

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| | 10/12/2018 Malte Backhaus | PIXEL2018 11

RD53 readout chip

μ = 64 e σ = 4 e

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| | 10/12/2018 Malte Backhaus | PIXEL2018 12

RD53 readout chip

RD53A Measurement vs. simulation

RD53A chip rate capability:

  • Measure hit processing efficiency as a

function of Xray flux

  • Buffer architecture optimized for

clusters, not for isolated Xray hits

  • 12.5 μs latency:
  • sensitive to digital buffer losses
  • 3.75 μs latency:
  • sensitive to dead time only
  • Expected to meet the design specs of

99% efficiency at 3.0 GHz/cm2 with clustered hits [TDR]  will measure in high rate particle beam More details:

  • D. Ruini, Serial Powering for the

Phase 2 upgrade of the CMS pixel detector

Xray

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Concept:

  • Simple design, ROC only active electronics on module

Constraints from geometry:

  • Both faces of TBPX ladders loaded with modules

 no service routing on back-side  supply current (and return) directly from module to module

  • TFPX and TEPX:

 service routing on “inactive” dee surface  current entries and exits module at the same side

  • Section dedicated module layout per detector section

10/12/2018 Malte Backhaus | PIXEL2018 13

Pixel Modules

1x2 2x2

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Prototype modules using RD53A

  • TBPX type HDI with aggressive design

produced:

  • Thin copper layers
  • Small pitch
  • RD53A modules build, first experience:
  • Design tested to 1kV sensor bias voltage
  • Current distribution and communication working
  • ROC performance as on PCB

Top layer, P = 200mW

Noise distribution on Module Noise with similar settings as on PCB. Charge and reference current not calibrated

μ = 67 e σ = 5 e

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Challenge  Solution  Consequence High occupancy  small/many/fast pixels  high supply current Long latency time  Large buffers, small feature size  high supply current

10/12/2018 Malte Backhaus | PIXEL2018 15

Serial Powering

Future CMS pixel detector requires ~50 kW / ~30kA on-detector power / supply current.  Power-loss in cables not tolerable. A reduction of factor 8-10 required. Serial powering is the only viable solution for powering Phase 2 pixels… ... never attempted before in a HEP experiment! Rcable very large due to ~100 m long cables

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Serial Powering

Across-module serial powering: Current “re-used” among n loads in series  Reduces current in cable resistances by n  System power efficiency increases with n2 Requires:

  • Constant total current constant  independent of actual load in chips
  • Defined current sharing among parallel chips  ohmic behavior of chips

Consequence:

  • Additional logic on chip  ShuntLDO
  • Enough current injected to satisfy highest loads

 any extra current (not used by load) gets burnt by shunts

  • Not sensitive to voltage drops  low cable cross section  low mass
  • Modules grounds / sensors bias differ inside a chain
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Serial Powering

10/12/2018 Malte Backhaus | PIXEL2018 17

  • Very active SP community across ATLAS and CMS
  • Quickly gaining experience and confidence
  • Still many developments ahead

Detailed talks:

  • S. Kuehn: Results of larger structures prototyping for the Phase-II upgrade of the pixel detector of the ATLAS experiment
  • D. Ruini: Serial Powering for the Phase 2 upgrade of the CMS pixel detector

Serial powering concept very reliable and robust

Pixel to pixel noise difference between parallel and serial powering mode VI-behavior of the first two RD53A modules

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TBPX support structure

Layer 2 Layer 3/4

Tmax – TCO2 [C] Tmax – TCO2 [C] TCO2 [C] TCO2 [C]

Layer 1

chip 1 fails chip 2 fails

Example of TBPX L3 module thermal modelling TBPX L1 cooling pipes driven below the chip hotspots

  • Thermal modelling
  • including all materials and interfaces
  • Improvements under study
  • Module power consumption including
  • Readout chips in normal operations and in failure modes
  • Sensor power consumption as function of fluence and

temperature

  • HDI

Tmax – TCO2 [C]

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| | 10/12/2018 Malte Backhaus | PIXEL2018 19

TFPX support structure

A ½ disk is composed of two Dees:

  • Odd dee: ring 1+ring 3
  • Even dee: ring 2+ring 4

Modules of arranged on both sides of a dee- "sandwich” structure CO2 cooling loop Carbon foam Carbon fibre skin Modules Modules

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| | 10/12/2018 Malte Backhaus | PIXEL2018 20

TEPX support structure

A disk is composed of one Dee with modules on both sides:

  • Odd side: ring 1 + 3 + 5
  • Even side: ring 2 + 4

Dee composed of symmetric sandwich:

  • Central layer  CO2 pipe and Airex foam
  • Module support plates:
  • Thermal: Thermal Pyrolytic Graphite
  • El. Isolation: Aluminium Nitride
  • Dee-PCB with electrical services
  • CFK panel
  • Modules

CFK PCB Airex PCB CFK

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| | 10/12/2018 Malte Backhaus | PIXEL2018 21

Expected performance

  • Comparable mass to CMS Phase 1 Inner Tracker
  • Slightly higher radiation lengths in barrel: 0.15 X/X0
  • Comparable in forward pixel (increase of number of layers)
  • Expanded to η = 4 due to extended pixel
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| | 10/12/2018 Malte Backhaus | PIXEL2018 22

Expected performance

  • Robust tracking in high pile-up environment
  • ~90% tracking efficiency up to 200 pile-up events until η = 3.8
  • Fake track rate below 0.02 (140 pile-up vertices) and 0.03 (200 pile-up vertices)
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  • Improved pT and impact parameter resolution wrt. Phase 1 tracker
  • Extended from η = 2.5 to η = 4

10/12/2018 Malte Backhaus | PIXEL2018 23

Expected performance

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| | 10/12/2018 Malte Backhaus | PIXEL2018 24

Summary

Many challenges for Phase 2 pixel detector & many ongoing developments:

  • Νew layout with extended forward coverage:
  • Ongoing TEPX layout under optimization incl. LUMI measurement
  • Electronics:
  • Radiation hard ROC
  • Demonstrator RD53A chip working, used for sensor R&D
  • All three analog Front-End prototypes meet specifications
  • Preparing for final CMS pixel chip submission (end of 2019)
  • Sensor R&D:
  • Intense R&D program, rapidly progressing since availability of ROC4SENS and RD53A chips
  • Investigating thin planar sensors structures, 3D for inner layer/ring, pixel aspect ratio
  • Modules:
  • Very first prototypes produced
  • Performance comparable to chips on PCBs
  • Novel methods:
  • Serial powering
  • Light stuctures
  • Easy installation
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Backup

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TBPX support structures

New way to split in 2 parts along z: 4 or 5 modules per layer (interleaved)

Layer 1 @ 30 mm Both faces of ladders loaded with modules no |η|= 0 projective gap