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TheAxonNetworkDevice: PrototypingwithNetFPGA JeffreyShafer,MikeFoss,Sco3Rixner,AlanL.CoxRiceUniversityJune2009 2
The Axon Network Device: Prototyping with NetFPGA
Jeffrey Shafer, Mike Foss, Sco3 Rixner, Alan L. Cox Rice University June 2009 Networks
Ethernet is a popular “plug and play” network Big challenge – scalability (i.e. broadcast) Big challenge – performance (i.e. spanning tree) June 20th, 2009 Jeffrey Shafer ‐ Rice University 2 ARPs are flooded! S S S S S S Redundant paths are disabled! Ethernet Switch (S) Locate H2 (ARP) Host H1 H2 Raising the Bar
Many researchers have proposed designs to solve Ethernet problems But, they evaluate their soluRons in simula'on We have designed a new network device (the Axon) that improves Ethernet and have built a prototype for evaluaRon The prototype proves that our design is pracIcal and implementable June 20th, 2009 Jeffrey Shafer ‐ Rice University 3 Axon Networks
Vision for a new network infrastructure Replace Ethernet switches with Axons Remove IP routers from network core Only used to communicate with other networks (their tradiRonal role) Hosts communicate with Axons via tradiRonal Ethernet Standard NICs, PHYs, protocols for full compaRbility Axons communicate with other Axons via a new protocol Source‐routed Ethernet Uses standard Ethernet physical layer (PHYs, cables) June 20th, 2009 4 Jeffrey Shafer ‐ Rice University Source‐Routed Ethernet
Backwards compaRbility with tradiRonal Ethernet Network appears to hosts as a giant switched Ethernet segment Transparent packet rewriRng Imagine sending packet from Host A to Host Z… First Axon on path strips standard header and replaces it with hop‐ by‐hop route list (“source route”) used for transport Final Axon restores the original header Axon design pushes complexity to the network edge State is stored by edge Axons Axons in network core only process the source routes Routes are determined by edge Axons (connected to host) Enables opportuniRes for the edge Axons to provide security or virtual networks by carefully choosing routes June 20th, 2009 5 Jeffrey Shafer ‐ Rice University 1 2 3 Data Source‐Routed Packet A Z Overview
Designed the Axon, a new network device Axons replace Ethernet switches, but are be3er (performance, scalability, …) Built Axon prototypes on exisRng NetFPGA pla`orm Easy to use + inexpensive Current work – Performance & Backwards CompaRbility Demonstrated using Axon prototype Future work – Network Scalability (up to 1 million hosts) Intend to demonstrate using a hybrid prototype/simulator infrastructure June 20th, 2009 6 Jeffrey Shafer ‐ Rice University Why Prototype?
Compelling demonstraRons Does the Axon architecture provides full compaRbility with unmodified hosts? Can we translate between tradiRonal Ethernet and source‐routed Ethernet at full network speed? (while using inexpensive / prac'cal hardware?) Compelling experiments How does the performance of Axons compare to Ethernet switches and IP routers when using real network hosts? June 20th, 2009 Jeffrey Shafer ‐ Rice University 7 Prototype Platform ‐ NetFPGA
Integrated development environment for network systems architecture research and educaRon Developed by team at Stanford Inexpensive ($499 academic price) Includes PCI board and FPGA reference designs 4‐port NIC, Ethernet Switch, and IP router Designs provide all soiware and hardware components, including Verilog and ModelSim libraries June 20th, 2009 Jeffrey Shafer ‐ Rice University 8 NetFPGA PCI Board
June 20th, 2009 Jeffrey Shafer ‐ Rice University 9 4‐port Gigabit Ethernet PHY SRAM Spartan FPGA Virtex‐II Pro 50 FPGA PCI Interface – 32‐bit, 33‐Mhz DDR Prototype Architecture ‐ Data Plane
Data Plane ‐ High‐speed packet forwarding on FPGA Reused exisRng NetFPGA components PCI card Verilog design library (e.g. DMA transfer engine) ModelSim test suite FPGA programming uRliRes Added new modules to FPGA (14,000 lines of Verilog) Cut‐through packet switching engine Input/output port units to transparently convert between tradiRonal and source‐routed Ethernet at line rate June 20th, 2009 10 Jeffrey Shafer ‐ Rice University Prototype Architecture ‐ Control Plane
Control Plane ‐ Management tasks on processor Intel Atom motherboard Low‐power + low‐cost + x86 compaRbility Don’t need a fast processor for control plane Reused exisRng NetFPGA components Linux (x86) device driver Programming and management tools Wrote new 6,000 line control program in C Determine network topology Calculate and establish source‐routes Manage Axon hardware June 20th, 2009 11 Jeffrey Shafer ‐ Rice University
Axon Prototype
June 20th, 2009 Jeffrey Shafer ‐ Rice University 12 Prototype Network
June 20th, 2009 Jeffrey Shafer ‐ Rice University 13 Data Plane Control Plane Axon Data Plane Control Plane Data Plane Control Plane Data Plane Control Plane Data Plane Control Plane Data Plane Control Plane A.P. Switch Gateway Router Host Host Host Campus / Public Internet Axon Unmodified devices Windows, Mac, Linux hosts Wireless A.P. Netgear switch Cisco router Standard protocols ARP, DHCP, Ethernet, … Transparent compaIbility! NetFPGA Advantages
Rapid development Leverage the Verilog library, ModelSim environment, and proven hardware The Axon prototype was a summer project Portability (x86‐based control soiware) Leverage this advantage for future simulator work June 20th, 2009 14 Jeffrey Shafer ‐ Rice University NetFPGA Drawbacks
Only 4 Ethernet ports – limits topologies FPGA is 76% full Prototype limited to 16‐entry CAM (CAM is used to translate between desRnaRon MAC address and source route at edge Axon) To show scalability on large networks, a much larger CAM would be needed (too big for FPGA) Have alternate design for prototype that uses a direct lookup method based on MAC address June 20th, 2009 15 Jeffrey Shafer ‐ Rice University
June 20th, 2009 Jeffrey Shafer ‐ Rice University 16Axon Hybrid Simulator
Network Scalability
How can we show that the Axon design scales to networks with 1 million+ hosts? Build / deploy vast numbers of prototypes? Propose a hybrid prototype / simulator infrastructure instead Use a few real hosts and real Axons Connect them to thousands of simulated Axons (which run the same x86 control soiware) June 20th, 2009 17 Jeffrey Shafer ‐ Rice University Hybrid Infrastructure
June 20th, 2009 18 Jeffrey Shafer ‐ Rice University Data Plane Control Plane Physical Axon Physical Host Simulator on server PC Control Plane Control Plane Control Plane Switchboard (MulRple Simulated Data Planes) Virtual Host Physical Links Virtual Links Virtual Host Virtual Host Example experiment: One physical host talks to thousands of virtual hosts via one physical Axon and thousands of virtual Axons How Does This Work?
Axons store state at edge of network Thus, many interesRng metrics are at the edge of the network and can be measured on the prototypes What do I use physical Axons for? IniRal verificaRon of simulator (inter‐operability and correctness) Measure Rming overhead to calibrate simulator How long does a route lookup take? Measure scalability of control soiware under real load Is an Atom processor sufficient to manage thousands of routes? June 20th, 2009 19 Jeffrey Shafer ‐ Rice University How Does This Work?
What do I use virtual Axons for? Measure how many bytes are sent/received to converge to a rouRng decision Measure how the control overhead increases compared to the network size Determine if the chosen routes efficiently traverse the network More interesRng network topologies (physical Axons only have 4 ports) Simulator machines will be memory‐limited, not processor‐limited Envision a dozen+ servers with 24GB RAM each June 20th, 2009 20 Jeffrey Shafer ‐ Rice University Axon Prototype Conclusions
Fully CompaRble … with exisRng hosts, switches, and routers PracRcal ImplementaRon … demonstrated network performance at line rate CompeRng network designs only use simulaRon Demonstrable Scalability Hybrid prototype / simulaRon infrastructure Thanks to Stanford NetFPGA development team – hap://necpga.org June 20th, 2009 21 Jeffrey Shafer ‐ Rice University
Questions? ?
June 20th, 2009 22 Jeffrey Shafer ‐ Rice University