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Mar 04, 2023 953 likes •1.21k views

Building the Adaptable Intelligent World Amit Gupta Vice President Software Engineering, Xilinx Inc Disruptive Innovation Transistor 1940s Computing 1970s Distributed Computing 1990s Mountains of One Architecture This is the Era

SLIDE 1

Building the Adaptable Intelligent World

Amit Gupta Vice President – Software Engineering, Xilinx Inc

SLIDE 2

Disruptive Innovation

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Transistor

1940s

SLIDE 4

1970s

Computing

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Distributed Computing

1990s

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This is the Era of Heterogeneous Compute One Architecture Can’t Do It Alone Mountains of Unstructured Data

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Software programmability Performance for a diverse range of applications Adaptability to keep pace with rapid innovation

Today’s Developer Needs

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CPUs Fixed Function Accelerators

ASICs/ASSPs/GPUs

FPGAs

Today’s Solutions

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Device Category

FPGA SoC MPSoC

Software Programmability

RFSoC

Disruptive Innovation Needed: Enter ACAP

A new class of devices for today’s challenges

ACAP

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ACAP

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daptive

mpute

cceleration latform A C A P

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Adaptive

Adaptive Hardware for Domain-specific Applications

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Adaptive Compute Acceleration

Adaptable Engines Scalar Engines Intelligent Engines

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Platform

ENABLING: Data Scientists SW App Developers HW Developers

Development Tools HW/SW Libraries Run-time Stack SW Programmable Silicon Infrastructure

SLIDE 15

Scalar Processing Engines

Versal ACAP Technology Tour

Adaptable Hardware Engines Intelligent Engines SW Programmable, HW Adaptable Breakout Integration of Advanced Protocol Engines

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Scalar Processing Engines

Arm Cortex-A72 Application Processor Arm Cortex-R5 Real-Time Processor Platform Management Controller

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Adaptable Hardware Engines

Re-architected foundational HW fabric for greater compute density Enables custom memory hierarchy 8X Faster Dynamic Reconfiguration (“on-the- fly”)

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Intelligent Engines

DSP Engines

High-precision floating point & low latency Granular control for customized datapaths

AI Engines

High throughput, low latency, and power efficient Ideal for AI inference and advanced signal processing

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AI Engines

Optimized for AI Inference and Advanced Signal Processing Workloads

>1GHz VLIW/SIMD vector processor cores Massive array of interconnected cores with local memory Tightly coupled to adaptable hardware enabling custom memory hierarchy Software programmable with hardware adaptability

VECTOR CORE MEMORY VECTOR CORE MEMORY VECTOR CORE MEMORY VECTOR CORE MEMORY

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Network-on-Chip (NoC)

Ease of Use

Inherently software programmable Available at boot, no place-and-route required

High Bandwidth and Low Latency

Multi-terabit/sec throughput Guaranteed QoS

Power Efficiency

8X power efficiency vs. soft implementations Arbitration across heterogeneous engines

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Comprehensive Tool Chain

USER TOOLS SUPPORTED ENTRY METHODS Data Scientists & AI Developers Frameworks Application Developers New Unified Software Development Environment Embedded Developers Embedded Run-Time Hardware Developers Vivado Design Suite

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Versal ACAP

Heterogeneous Acceleration For Any Application For Any Developer

Delivers

Disruptive Innovation Software Programmability Hardware Adaptability Whole Application Acceleration

IN SUMMARY

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