Tasks & Memory Management October 30, 2007 Contents Task - - PDF document

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Faculty of Computer Science Institute for System Architecture, Operating Systems Group Tasks & Memory Management October 30, 2007 Contents Task creation Address space setup Page-fault handling Pager Hierarchical

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SLIDE 1

Faculty of Computer Science Institute for System Architecture, Operating Systems Group

October 30, 2007

Tasks & Memory Management

TU Dresden, 30.10.07 Slide 2

Contents

  • Task creation
  • Address space setup

– Page-fault handling – Pager – Hierarchical address spaces

  • Virtual memory management

– Region Mapper

  • Dataspaces
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SLIDE 2

TU Dresden, 30.10.07 Slide 3

So far…

Kernel

Fiasco Microkernel

Root Task Sigma0

Root Pager

  • BIOS started, loaded and executed boot sector
  • GRUB loaded kernel and boot modules
  • Bootstrap interpreted binary modules and set up kernel

structures (Kernel Info Page)

  • Kernel started by Bootstrap
  • Root task and Sigma0 (initial address space) started by

kernel  Next step: start application tasks

TU Dresden, 30.10.07 Slide 4

Task Creation

l4_task_new System call:

l4_taskid_t l4_task_new ( l4_taskid_t destination, /* destination task id */ l4_umword_t mcp_or_new_chief, /* maximum controlled priority * or new chief */ l4_umword_t esp, /* stack pointer of first thread */ l4_umword_t eip, /* instruction pointer of first * thread */ l4_threadid_t pager /* pager of first thread */ );

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SLIDE 3

TU Dresden, 30.10.07 Slide 5

Task Creation

Kernel

Fiasco Microkernel

Root Task Sigma0

Root Pager

l4_task_new(…, esp, eip, rmgr_pager) Kernel Area 4GB 3GB esp eip

TU Dresden, 30.10.07 Slide 6

Task Creation

Kernel

Fiasco Microkernel

Root Task Sigma0

Root Pager

Kernel Area 4GB 3GB Stack Code Data esp eip

Task needs to access code / data / stack / … to execute application

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SLIDE 4

TU Dresden, 30.10.07 Slide 7

Task Creation

CPU tries to fetch instruction at eip  Page-fault exception

Kernel

Fiasco Microkernel

Root Task Sigma0

Root Pager

Kernel Area 4GB 3GB esp eip

TU Dresden, 30.10.07 Slide 8

Page-Fault Handling

  • Page-fault exception is

caught by kernel page-fault handler

  • No management of user

memory in kernel

  • Invoke user-level memory

management  Pager

eip

Application’s address space

Kernel

Fiasco Microkernel

Page-Fault Handler

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SLIDE 5

TU Dresden, 30.10.07 Slide 9

Pager

Application’s address space Pager’s address space

Pager Memory Pager Code Kernel

Fiasco Microkernel

Page-Fault Handler

  • Thread which is invoked on page fault
  • Each thread has a (potentially different) pager assigned

TU Dresden, 30.10.07 Slide 10

Pager Invocation

  • Communication with pager thread  IPC
  • Kernel page-fault handler sets up IPC to pager
  • Pager sees faulting thread as sender of IPC

Pager’s address space

Pager Memory Pager Code

Application’s address space

Kernel

Fiasco Microkernel

Page-Fault Handler

call(…,fault address, fault eip,…)

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SLIDE 6

TU Dresden, 30.10.07 Slide 11

Page-Fault IPC

Short IPC (register-only transfer):

dw0 (EDX) dw1 (EBX) fault address / 4 (30) faulting EIP (32) w ~ w = 0 read page fault w = 1 write page fault

Pager’s address space

send base write grant flexpage page address(20) size(6) ~(4)

Pager should reply with Flexpage IPC:  Maps one or more pages from pager address space to application address space

TU Dresden, 30.10.07 Slide 12

Page-Fault Handling

  • Pager maps pages of his own address space into the

client address space

Kernel

Fiasco Microkernel

Page-Fault Handler

Pager’s address space

Pager Memory Pager Code

Application’s address space

send(app_id,fpage(..),…)

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SLIDE 7

TU Dresden, 30.10.07 Slide 13

Page Mapping

Kernel

Fiasco Microkernel Pager’s address space Application’s address space Memory Page Frames Virtual Memory Virtual Memory

send(…, fpage, ..)

  • Entry in virtual memory points to page frame in phys. memory

 Map creates an entry in the receiver’s address space pointing to the same page frame  Only valid entries in pager’s address space can be mapped to clients

TU Dresden, 30.10.07 Slide 14

  • Special case: grant pages

Page Mapping

Kernel

Fiasco Microkernel Pager’s address space Application’s address space Memory Page Frames Virtual Memory Virtual Memory

send(…, fpage, ..)

 Removes mapping in sender's address space

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SLIDE 8

TU Dresden, 30.10.07 Slide 15

  • Unmap removes entries to a page frame (fpage is specified in the

invoker's address space)

Page Mapping

Kernel

Fiasco Microkernel Pager’s address space Application’s address space Memory Page Frames Virtual Memory Virtual Memory

unmap(fpage)

 Kernel needs to keep track, which page frames are mapped in which address space  Mapping Database

TU Dresden, 30.10.07 Slide 16

Flexpage IPC in Detail

  • Flexpages describe areas in address spaces (size aligned)
  • Flexpage size 2size, smallest is hardware page (4KByte on IA32)
  • Both source pages and target area of a map IPC are flexpages

Sender’s Address Space Receiver’s Address Space send base(32) page address(20) size(6) ~(4)

wg

page address(20) size(6) ~(4)

wg

l4_ipc_receive(…)

Receive Window

l4_ipc_send(…)

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SLIDE 9

TU Dresden, 30.10.07 Slide 17

Flexpage IPC in Detail send base

Send flexpage is smaller than the receive window

– Target position in receive window is derived from page alignment and send base

send base(32) page address(20) size(6) ~(4)

w g

l4_ipc_send(…)

page address(20) size(6) ~(4)

w g

l4_ipc_receive(…)

TU Dresden, 30.10.07 Slide 18

Flexpage IPC in Detail send base

Send flexpage is larger than receive window

– Source position in send flexpage is derived from page alignment and send base

send base(32) page address(20) size(6) ~(4)

w g

l4_ipc_send(…)

page address(20) size(6) ~(4)

w g

l4_ipc_receive(…)

 send base is a hot spot for mapping IPC  Actual send base depends on information about the receiver

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SLIDE 10

TU Dresden, 30.10.07 Slide 19

Application's Address Space Pager’s Address Space page address(20) 12 ~(4) send base  pf address

Page-Fault IPC in Detail

  • Kernel Page-Fault handler sets receive window to whole

address space  Pager can map more than just the page where the page fault happened to the client

Kernel

Fiasco Microkernel

Page-Fault Handler

32 ~ Page-Fault Receive Window

TU Dresden, 30.10.07 Slide 20

Task Creation

 Roottask is the pager of applications loaded as grub modules  Roottask requests memory from Sigma0, which initially owns all memory

Kernel

Fiasco Microkernel Root Task’s address space Roottask App Code Section App Data Section Memory Application’s address space

l4_task_new(…) esp eip

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SLIDE 11

TU Dresden, 30.10.07 Slide 21

Task Creation

Kernel

Fiasco Microkernel Root Task’s address space Roottask App Code Section App Data Section Memory Application’s address space Stack Code Data

  • Pages are mapped as they are needed

 Demand Paging

TU Dresden, 30.10.07 Slide 22

Breakpoint

  • Task Creation / Basic Page-Fault Handling

– Roottask starts tasks for all boot modules Can start basic L4Env services

  • Flexpage IPC
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SLIDE 12

TU Dresden, 30.10.07 Slide 23

Hierarchical Pager

  • Initial pager can only implement basic memory

management No knowledge about application requirements

– Different requirements at the same time

No services available to implement more advanced memory management

– No disk driver

Build more advanced pagers on top of the initial pager  Pager hierarchies

TU Dresden, 30.10.07 Slide 24

Hierarchical Pager

Initial Address Space

  • Phys. Memory

1-to-1 mapped

Kernel

Fiasco Microkernel

Pager 1 Pager 2 Pager 3 Disk Driver Application Application

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SLIDE 13

TU Dresden, 30.10.07 Slide 25

Hierarchical Pager Real World Example

  • L4Linux implements Linux paging policy
  • DROPS pager implements Real-Time paging policy

(no swapping etc.)

Initial Address Space

  • Phys. Memory

1-to-1 mapped

Kernel

Fiasco Microkernel Linux Paging Linux Swap

L4Linux Kernel Server

L4Linux Applications L4Linux Applications

DROPS Pager

Real-Time Applications Real-Time Applications

TU Dresden, 30.10.07 Slide 26

Virtual Memory Management

  • Pager must specify send base

 Pager needs to know client’s address space layout –

  • k if only one pager manages the address space

(e.g. L4Linux)  Virtual memory must be managed independently of pagers

Initial Address Space

  • Phys. Memory

Kernel Pager 1 Pager 2 Pager 3 Disk Driver Application Application

  • Possible conflicts if more than one pager manages an address

space:

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SLIDE 14

TU Dresden, 30.10.07 Slide 27

Region Map

  • Per-address space map that keeps track which part of the

address space is managed by which pager:

Address space Pager 1 Pager 2 Pager 2

<start, end> Pager 1 Pager 2 VM Region Pager <start, end> <start, end> Region Map Pager 2

TU Dresden, 30.10.07 Slide 28

Region Mapper

  • Intermediate pager which identifies which pager should handle a

page fault

  • Can reside in the application’s address space or in an external task

Application Pager 1

Kernel

Fiasco Microkernel

Page-Fault Handler

Region Mapper Pager 1 Pager 2 Pager 2 <start, end> Pager 1 Pager 2 VM Region Pager <start, end> <start, end> Pager 2 Pager Code Pager Memory

call( region mapper, pf addr, pf eip, …)

 Region Mapper is pager of all other threads of a task

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SLIDE 15

TU Dresden, 30.10.07 Slide 29

Region Mapper

  • Region Mapper calls the real pager, restricts receive

window to area which is managed by that pager  No interference between different pagers

Application Pager 1

Kernel

Fiasco Microkernel

Page-Fault Handler

Region Mapper Pager 1 Pager 2 Pager 2 <start, end> Pager 1 Pager 2 VM Region Pager <start, end> <start, end> Pager 2 Pager Code Pager Memory

call(pager1, pf addr, pf eip, receive window, …)

TU Dresden, 30.10.07 Slide 30

Breakpoint

  • Task Creation / Basic Page-Fault Handling

– Roottask starts tasks for all boot modules Can start basic L4Env services

  • Flexpage IPC
  • Hierarchical Pagers
  • Virtual Memory Management  Region Mapper
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SLIDE 16

TU Dresden, 30.10.07 Slide 31

High-Level Memory Abstraction

  • Memory management in terms of pages so far
  • Application’s view to memory

– Code / data sections – Memory mapped files – Anonymous memory (heaps, stacks, …) – Network / file system buffers – etc….

Abstraction to map this view to low-level memory management

TU Dresden, 30.10.07 Slide 32

Dataspaces

  • Dataspace: unstructured data container
  • Abstraction for anything that contains data:

– Files – Anonymous memory – I/O adapter memory – etc…

  • Dataspaces are implemented by Dataspace

Managers

  • Dataspaces can be attached to regions of an

address space

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SLIDE 17

TU Dresden, 30.10.07 Slide 33

Dataspace Manager

  • A Dataspace Manager determines the semantic of a dataspace
  • Each Dataspace Manager is the pager for its dataspaces

 Implements the paging policy (page replacement etc.)

Dataspace Manager’s Address Space Dataspace Manager’s Memory Dataspaces ds1 ds2

TU Dresden, 30.10.07 Slide 34

Dataspaces & Region Mapper

  • Region map keeps track which dataspaces are attached to which

VM regions

  • Region mapper translates page faults to dataspace faults:

pf (addr)  dataspace fault (dataspace manager, id, offset)  Dataspace manager provides fault handler to map pages

Application’s Address Space Dataspace Manager’s Address Space Dataspace Manager’s Memory Dataspaces ds1 ds2 <start, end> Dataspace Manager 1, 1 Dataspace Manager 2, 1 VM Region Dataspace <start, end> <start, end> Dataspace Manager 2, 2 Region Map Dataspace Manager 1 Dataspace 1 Dataspace Manager 2 Dataspace 1 Dataspace Manager 2 Dataspace 2

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SLIDE 18

TU Dresden, 30.10.07 Slide 35

Application’s View to Dataspaces

  • Open / Close dataspaces

– Create / destroy dataspace – Semantic depends on dataspace type: – anonymous memory: open (size)  dataspace id – file: open (filename, mode, …)  dataspace id – etc.

  • Attach / Detach dataspace

– Create / remove entry in region map  Makes dataspace contents accessible to application

  • Share / Revoke

– Grant / remove access rights to other applications  Very easy shared memory implementation

TU Dresden, 30.10.07 Slide 36

Application Address Spaces

  • Address spaces of applications are constructed from several

dataspaces:

Application’s Address Space Code RO Data Data BSS Mmap’ed File Stack File System Memory Manager Memory Files-System Buffers

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SLIDE 19

TU Dresden, 30.10.07 Slide 37

Breakpoint

  • Task Creation / Basic Page-Fault Handling

– RMGR starts tasks for all boot modules – Can start basic L4Env services

  • Hierarchical Pagers
  • Virtual Memory Management  Region Mapper
  • High-Level Memory Abstraction: Dataspaces

TU Dresden, 30.10.07 Slide 38

Other Issues in Memory Management

  • Page Allocation Algorithms

– List-based Algorithms, bitmaps, trees, …

  • Page Replacement Algorithms

– Least-Recently-Used (LRU) – Working Sets – Clock – …

Both page allocation and page replacement are implemented by dataspace managers Can have different strategies for the dataspaces of an application

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SLIDE 20

TU Dresden, 30.10.07 Slide 39

Other Issues in Memory Management

  • User-level memory allocation (malloc)

Implemented by C-library, based on mmap / sbrk Mapped to dataspaces containing anonymous memory

TU Dresden, 30.10.07 Slide 40

Memory Sharing

  • Memory sharing important for

– Shared libraries – Data transfer between system components – …

  • Different types of sharing

Full sharing, all clients see modifications Easy to implement, pager / dataspace manager grants access rights to pages / dataspaces

Lazy copying of dataspaces Read-only access to dataspace, copy only on write access Copy-on-write

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SLIDE 21

TU Dresden, 30.10.07 Slide 41

Cache Management

CPU L1 Cache L2 Cache Main Memory 1 cycle ~10 cycles ~50 cycles

Why manage caches?

  • Cache access times (PIII 450 MHz):

Caches significantly influence execution times Cache misses increases worst-case execution times in real-time systems

TU Dresden, 30.10.07 Slide 42

Cache Architecture

  • Cache lookup either with virtual or physical addresses
  • Virtual or physically indexed / tagged caches

Cache valid tag cache line valid tag cache line valid tag cache line cache line

  • ffset

cache line index tag Address valid tag cache line

=

valid tag cache line

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SLIDE 22

TU Dresden, 30.10.07 Slide 43

Cache Associativity

  • N-way associative cache: index points to a set of n cache lines

v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line cache line

  • ffset

cache line index tag Address

=

v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line v tag cache line

TU Dresden, 30.10.07 Slide 44

Cache Architecture Address to cache-line mapping

Cache v tag cache line v tag cache line v tag cache line v tag cache line Index 1 2 3 Memory 1 2 3 1 1 1 1 2 1 3 v tag cache line v tag cache line v tag cache line v tag cache line 1 2 3 1 1 1 1 2 1 3

 Address determines cache line set  Can be used by memory management to allocate cache partitions  Cache / Memory colors

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SLIDE 23

TU Dresden, 30.10.07 Slide 45

OS-Controlled Cache Partitioning

  • Control color of memory pages during allocation
  • Problems:

– works only for physically tagged / indexed caches – allocation with page granularity:

 Cache line index + cache line offset must be larger than page offset:

– cache line offset  cache line size – cache line index 

page offset (12) page address (20) cache line

  • ffset

tag cache line index

controlled by memory management

cache size cache line size × associativity

TU Dresden, 30.10.07 Slide 46

OS-Controlled Cache Partitioning

  • Pentium III (physically tagged, physically indexed caches):

– 16KB L1 cache – 4-way set associative – 256KB L2 cache – 8-way set associative – 32 byte cache lines, 4KB Pages

  • Cache line offset L1/L2: 5 bit
  • Cache line index:

– L1   7 bit index – L2   10 bit index

16 KByte 32 Byte ×4 = 128

256 KByte 32 Byte × 8 = 1024

page offset (12) page address (20)

  • ffset(5)

tag index(7)

  • ffset(5)

tag index(10)

 23 = 8 colors in L2 cache

  • Phys. Address

L1 L2

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SLIDE 24

TU Dresden, 30.10.07 Slide 47

OS-Controlled Cache Partitioning

Assign different memory colors to subsystems to avoid interferences

Initial Address Space Memory

Linux Paging Linux Swap

L4Linux Kernel Server DROPS Pager

L4Linux Applications L4Linux Applications Real-Time Applications Real-Time Applications

TU Dresden, 30.10.07 Slide 48

More Information

  • Flexpages
  • H. Härtig, J. Wolter, J. Liedtke: “Flexible sized page objects” ,

http://os.inf.tu-dresden.de/papers_ps/flexpages.pdf

  • Dataspaces

Mohit Aron, Yoonho Park, Trent Jaeger, Jochen Liedtke, Kevin Elphinstone, Luke Deller: “The SawMill Framework for VM Diversity”, ftp://ftp.cse.unsw.edu.au/pub/users/disy/ papers/Aron_PJLED_01.ps.gz

  • Cache Partitioning
  • J. Liedtke, H. Härtig, M. Hohmuth: “OS-Controlled Cache

Predictability for Real-Time Systems”, http://os.inf.tu-dresden.de/papers_ps/rtas97.pdf