T15: 402.8.3 Off Detector Electronics Colin Jessop, University of - PowerPoint PPT Presentation

T15: 402.8.3 – Off Detector Electronics Colin Jessop, University of Notre Dame US-MTD Technical Review 15-16 November 2018

Outline § Requirements § Design § R&D and prototyping plan, maturity, milestones § Production-era: QA and QC testing plan § Risks § Value Engineering § Summary Y. Name – Talk Title US-MTD Technical Review 2

Biographical sketch § Colin Jessop, Professor at University of Notre Dame § Role in MTD/US-MTD – proponent of using the Barrel calorimeter OD boards in the MTD § Relevant experience iCMS L2 manager for HL-LHC Barrel Calorimeter Upgrade USCMS L2 manager for HL-LHC Barrel Calorimeter ( Main scope is the off-detector electronics. Proposal is to use the same boards for MTD) This is potential upscope. Toyoko Orimoto (Northeastern will be the L4 manager if this occurs) Y. Name – Talk Title US-MTD Technical Review 3

Off Detector Electronics Requirements § Receive data from front-end on 5 Gb/s optical links (lpGBT in low power mode) § Perform feature extraction, data concentration. § Pass data to CMS DAQ via 16 Gb/s optical links § Provide clock and control from trigger and DAQ throttles through lpGBT control links § Meet Advanced Telecommunciation Architecture standards (ATCA) adopted by iCMS § Clock distribution should introduce < 10ps jitter. § iCMS wants same boards in Barrel and endcap but not a technical requirement (other detectors have different boards) Y. Name – Talk Title US-MTD Technical Review 4

BTL/ETL Front-end Readout Endcap Barrel ROC (FE ASIC) 16 or 32 channels per • 6 TOFHIR (FE ASIC) per TOFHIR board • ROC 192 Channels per TOFHIR board 16 ROC’s per module • One concentrator card (CC) serves • 168 modules per octant • four TOFHIR Boards (768 Channels) 2624 modules (16 octants) • Nine CC’s per tray and 72 trays • 1 LpGBT per 2 modules to • 648 CC boards with 1 lpGBT per CC • give 1312 lpGBT’s Max 3.0 Gb/s for each module • 1.9 Gb/s for each CC • (1.4 Tb/s per endcap) Barrel Concentrator Card 72 trays with 9 modules • Y. Name – Talk Title US-MTD Technical Review 5

Barrel Timing Layer Concentrator Card Barrel Each CC has one lpGBT Endcap 1 lpGBT per two modules LpGBT controls a versalink+ with one TX (data) and RX (control) optical link. Total of 1296 optical links from barrel. In endcap 2624 optical links. Y. Name – Talk Title US-MTD Technical Review 6

Barrel and Endcap Timing Processor Design for ECAL/HCAL barrel in • NSF scope ▪ Two Kintex Ultrascale XKCU115 • FPGA’s ▪ ECAL/HCAL uses lpGBT’s (~13000 • @ 10 Gb/s) 112 bi-directional links available • @ up to 16 Gb/s Control links @ 2.4 Gb/s to • front-end ▪ Links to DAQ @ 16Gb/s • Required to provide clock < 10ps • ▪ jitter (BCAL spec is 30ps @ 50 GeV) Barrel Calorimeter Barrel Calorimeter processor(BCP) becomes BTP/ETP for MTD Y. Name – Talk Title US-MTD Technical Review 7

DAQ DTH board CERN developed ATCA DAQ board • to be used in all detectors Two versions • DTH400 400 Gb/s • DTH800 800 Gb/s • DTH sits in OD crates with BTP/ETP • board BTL/ETL OD architecture must • match bandwidth of DTH Y. Name – Talk Title US-MTD Technical Review 8

Proposed Architecture & Deliverables Barrel One processor board (BTP) for each 8 trays Endcap One processor board (ETP) per octant Item #CMS #spares/test #total stands Barrel BTP 9 2 11 DTH400 1 1 2 DTH800 1 1 2 Crate 1 1 2 Endcap ETP 16 2 18 DTH800 4 1 5 Crate 2 1 3 Total of 29 processor boards, 9 DTH boards and 5 ATCA crates Y. Name – Talk Title US-MTD Technical Review 9

Labor § The labor and management cost for the development of BCP and associated firmware is already fully covered in NSF scope § Engineering technical support for MTD specific issues @ 0.2 FTE/year 2019-2023 § System tests and software can be done by physicists with technical support from engineer. Y. Name – Talk Title US-MTD Technical Review 10

BTP/ETP Schedule MREFC Funding Start PDR FDR MREFC Completion CDR CY20 CY17 CY18 CY19 CY21 CY22 CY23 CY24 CY26 CY16 CY25 Design and Development (under operations program) Pre-Production BTP/ ETP Production Testing and Integration Schedule Float Int’l Need- by-date PRR CMS TDR EDR LHC LS 2 Run 4 Run 2 Run 3 LS 3 HL-LHC Operations Start V1.1 Nov 19 , 2017 The BTP/ETP follows the BCP schedule which began in CY17 Y. Name – Talk Title US-MTD Technical Review 11

OD Schedule compared to project Prototype 1 boards available Prototype 2 boards available Preproduction boards availabl e Production boards available Y. Name – Talk Title US-MTD Technical Review 12

R&D Schedule and milestones Milestone Date Status BCP specified Q1 2018 Complete ECAL demo chain tested Q4 2017 Complete HCAL demo chain tested Q2 2018 Complete MTD OD architecture specified Q1 2019 BTP/ETP demo board available Q2 2019 BTP/ETP demo chain tested Q4 2019 BTP/ETP Prototype available Q4 2020 BTP/ETP Proto chain tested Q2 2021 BTP/ETP Production ready Q1 2022 Follows the NSF BCP development allowing time for MTD specific readout chain tests Y. Name – Talk Title US-MTD Technical Review 13

Production QA/QC § We will produce 154 BCP boards for ECAL/HCAL § Propose to build an extra 29 for MTD § Detailed QA/QC plan is being prepared for NSF FDR in 2019 Y. Name – Talk Title US-MTD Technical Review 14

Risks § The most significant risk presently is the possibility of changes in the front-end readout which change the #channels and bandwidth (RT-402-8-39-D) § Assign a 50% probability that the number of BTP/ETP boards is increased by 30% in next 2 years § This is a cost risk: 9 extra boards + DTH + crate § Technical risks are low since OD electronics can be fixed and US has extensive experience. Y. Name – Talk Title US-MTD Technical Review 15

Value Engineering § By using the BCP for the MTD we save on development and management costs for board development (~$2M+contingency) which are already covered in NSF scope § Total project cost of ~$1M+contingency is around 1/3 of normal cost for this project Y. Name – Talk Title US-MTD Technical Review 16

Summary § Proposal to use BCP for MTD has many pro’s § Enhances US intellectual contribution § Value engineers across projects § US will design all of readout chain in ETL and everything in BTL except FE ASIC lowering overall risk § Provides low risk, cheap core contribution § Con’s § Technically there is no downside § Status : A potential upscope at this point (~10% upscope in total project cost would cover it) Y. Name – Talk Title US-MTD Technical Review 17