T15: 402.8.3 Off Detector Electronics Colin Jessop, University of - - PowerPoint PPT Presentation
T15: 402.8.3 Off Detector Electronics Colin Jessop, University of - - PowerPoint PPT Presentation
T15: 402.8.3 Off Detector Electronics Colin Jessop, University of Notre Dame US-MTD Technical Review 15-16 November 2018 Outline Requirements Design R&D and prototyping plan, maturity, milestones Production-era: QA and QC
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§ Requirements § Design § R&D and prototyping plan, maturity, milestones § Production-era: QA and QC testing plan § Risks § Value Engineering § Summary
Outline
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§ Colin Jessop, Professor at University of Notre Dame § Role in MTD/US-MTD – proponent of using the Barrel calorimeter OD boards in the MTD § Relevant experience iCMS L2 manager for HL-LHC Barrel Calorimeter Upgrade USCMS L2 manager for HL-LHC Barrel Calorimeter (Main scope is the off-detector electronics. Proposal is to use the same boards for MTD) This is potential upscope. Toyoko Orimoto (Northeastern will be the L4 manager if this occurs)
Biographical sketch
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§ Receive data from front-end on 5 Gb/s optical links (lpGBT in low power mode) § Perform feature extraction, data concentration. § Pass data to CMS DAQ via 16 Gb/s optical links § Provide clock and control from trigger and DAQ throttles through lpGBT control links § Meet Advanced Telecommunciation Architecture standards (ATCA) adopted by iCMS § Clock distribution should introduce < 10ps jitter. § iCMS wants same boards in Barrel and endcap but not a technical requirement (other detectors have different boards)
Off Detector Electronics Requirements
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BTL/ETL Front-end Readout
Barrel
- 6 TOFHIR (FE ASIC) per TOFHIR board
192 Channels per TOFHIR board
- One concentrator card (CC) serves
four TOFHIR Boards (768 Channels)
- Nine CC’s per tray and 72 trays
- 648 CC boards with 1 lpGBT per CC
- 1.9 Gb/s for each CC
- 72 trays with 9 modules
Barrel Concentrator Card
Endcap
- ROC (FE ASIC) 16 or 32 channels per
ROC
- 16 ROC’s per module
- 168 modules per octant
- 2624 modules (16 octants)
- 1 LpGBT per 2 modules to
give 1312 lpGBT’s
- Max 3.0 Gb/s for each module
(1.4 Tb/s per endcap)
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Barrel Timing Layer Concentrator Card
LpGBT controls a versalink+ with one TX (data) and RX (control) optical link. Total of 1296 optical links from barrel. In endcap 2624 optical links. Barrel Each CC has one lpGBT Endcap 1 lpGBT per two modules
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Barrel and Endcap Timing Processor
▪ ▪ ▪ ▪
Barrel Calorimeter
- Design for ECAL/HCAL barrel in
NSF scope
- Two Kintex Ultrascale XKCU115
FPGA’s
- ECAL/HCAL uses lpGBT’s (~13000
@ 10 Gb/s)
- 112 bi-directional links available
@ up to 16 Gb/s
- Control links @ 2.4 Gb/s to
front-end
- Links to DAQ @ 16Gb/s
- Required to provide clock < 10ps
jitter (BCAL spec is 30ps @ 50 GeV) Barrel Calorimeter processor(BCP) becomes BTP/ETP for MTD
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DAQ
DTH board
- CERN developed ATCA DAQ board
to be used in all detectors
- Two versions
- DTH400 400 Gb/s
- DTH800 800 Gb/s
- DTH sits in OD crates with BTP/ETP
board
- BTL/ETL OD architecture must
match bandwidth of DTH
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Proposed Architecture & Deliverables
Item #CMS #spares/test stands #total Barrel BTP 9 2 11 DTH400 1 1 2 DTH800 1 1 2 Crate 1 1 2 Endcap ETP 16 2 18 DTH800 4 1 5 Crate 2 1 3 Barrel One processor board (BTP) for each 8 trays Endcap One processor board (ETP) per octant Total of 29 processor boards, 9 DTH boards and 5 ATCA crates
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§ The labor and management cost for the development of BCP and associated firmware is already fully covered in NSF scope § Engineering technical support for MTD specific issues @ 0.2 FTE/year 2019-2023 § System tests and software can be done by physicists with technical support from engineer.
Labor
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BTP/ETP Schedule
V1.1 Nov 19 , 2017
MREFC Funding Start
CY18 CY17 CY19 CY20 CY21 CY22 CY23 CY24
Design and Development (under operations program) Production
CY25 CY26 CY16
CDR PDR FDR
Int’l CMS
TDR EDR Need- by-date
LHC
Run 2 Run 3 Run 4 LS 2 LS 3
HL-LHC Operations Start MREFC Completion
Schedule Float Pre-Production Testing and Integration BTP/ ETP
PRR
The BTP/ETP follows the BCP schedule which began in CY17
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OD Schedule compared to project
Preproduction boards available Production boards available Prototype 1 boards available Prototype 2 boards available
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R&D Schedule and milestones
Milestone Date Status BCP specified Q1 2018 Complete ECAL demo chain tested Q4 2017 Complete HCAL demo chain tested Q2 2018 Complete MTD OD architecture specified Q1 2019 BTP/ETP demo board available Q2 2019 BTP/ETP demo chain tested Q4 2019 BTP/ETP Prototype available Q4 2020 BTP/ETP Proto chain tested Q2 2021 BTP/ETP Production ready Q1 2022
Follows the NSF BCP development allowing time for MTD specific readout chain tests
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§ We will produce 154 BCP boards for ECAL/HCAL § Propose to build an extra 29 for MTD § Detailed QA/QC plan is being prepared for NSF FDR in 2019
Production QA/QC
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§ The most significant risk presently is the possibility
- f changes in the front-end readout which change
the #channels and bandwidth (RT-402-8-39-D) § Assign a 50% probability that the number of BTP/ETP boards is increased by 30% in next 2 years § This is a cost risk: 9 extra boards + DTH + crate § Technical risks are low since OD electronics can be fixed and US has extensive experience.
Risks
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§ By using the BCP for the MTD we save on development and management costs for board development (~$2M+contingency) which are already covered in NSF scope § Total project cost of ~$1M+contingency is around 1/3 of normal cost for this project
Value Engineering
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