Status of DUNE DAQ Hardware/Firmware Development Status David - - PowerPoint PPT Presentation

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Status of DUNE DAQ Hardware/Firmware Development Status David Cussans DUNE DAQ Meeting 15 th October, 2018 Introduction Concentrating on firmware Agnostic of where it is implemented For TDR firmware will be demonstrated on

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SLIDE 1

Status of DUNE DAQ Hardware/Firmware Development Status

David Cussans DUNE DAQ Meeting 15th October, 2018

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SLIDE 2

Introduction

  • Concentrating on firmware

Agnostic of where it is implemented

  • For TDR firmware will be demonstrated on commercial

development boards.

ZCU102 chosen

  • Initially, will use FPGA on Dev board to store data/patterns
  • Move to external data source

Commonality with BNL plans for slice test

Presenter Name | Presentation Title 2

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SLIDE 3

Firmware Development

  • See minutes, recording at https://indico.fnal.gov/event/18658/
  • CERN GitLab area set up:

https://gitlab.cern.ch/DUNE-SP-TDR-DAQ/dataflow-firmware

Accessible to all DUNE collaborators (avoiding issues with FNAL Redmine)

Let me know if access problems

 Blocks:

Framework ( D Newbold , Bristol/RAL )

Filtering, pedestal subtraction ( K Manolopoulos , RAL)

Hit finding ( K Kothekar , Bristol)

Compression ( G Iles , P Dunn , Imperial)

 Platform: Porting IPBus reference design to ZCU102 ( K Harder , RAL)

Presenter Name | Presentation Title 3

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SLIDE 4

Framework ( D Newbold )

 Changed interface between processing blocks to use an AXI4-Stream based interface.  An example design is now present in the repository that streams data through processing

  • blocks. ( All the blocks do is sum up the samples in each block and output the sum )

 Following E-mail discussion about how to handle overflow, it looks like each packet will

need a trailer. ( So the structure of each packet will be header,payload,trailer )

 Simulation almost works. Hampered by DMN and Alessandro Thea hitting a Modelsim bug.  Todo:  Writing pipelinng stages that will allow the insertion of registers. ( Difficult, due to the

hand-shaking ). DMN to tackle

 Create empty top level design for synthesis (DMN)  Write down documentation for assumptions about data structures - i.e. each channel

should be independent. Packets of data flowing down each channel should be time

  • rdered.

 Write and document scripts to load (simulated) ADC data into framework, play it

thorough processing blocks and retrieve output (Jim Brooke, et. al.)

Presenter Name | Presentation Title 4

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SLIDE 5

4k deep (12bit) 32bit wide LUT Only 18bits used for encoding 4k deep (12bit) 32bit wide LUT Only 18bits used for encoding Packer Packer 32bit to 4bit FIFO 32bit to 4bit FIFO Flow Control Flow Control Implemented Packer in KU115 at 320MHz (didn’t try to go faster). Seems OK, but not tested. Compression block is fairly generic. Can replace Fibonacci with another compression scheme if required. Proposal: Sacrifjce top 16 words (e.g. 4095-4080) to provide control words (e.g. overfmow, recovery, back-to-normal- data-fmow, etc). The control words could be followed by a subsequent words to provide info (albeit limited to 11 rather than 12bit for obvious reasons) e.g. number of missed samples during

  • verfmow conditjon.

Full?

Compression ( G Isles , P Dunne )

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SLIDE 6
  • Self contained tests starting in hardware

AWVALID, WVALID, WLAST, WSTROBE

10-Second Buffer ( E Motuk, UCL )

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SLIDE 7
  • Things to do:
  • Currently the data packets are sent by toggling a VIO
  • utput bit – One packet is sent at each rising transition
  • Continuous packet sending will be implemented
  • Currently the read operation flows the write operation –

for debugging the correct writing

  • The read operation will start after a certain time
  • Flow control signals for this type of operation are

already implemented

  • An additional FIFO will be added to keep track of the

write addresses for each packet

  • The output control block will be fleshed out

10-Second Buffer ( E Motuk, UCL )

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SLIDE 8

F a s t H i t F i n d e r ( K K

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h e h a r , B r i s t

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)

S t a r t f r

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p e d e s t a l

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u b t r a c t e d A D C s a mp l e s , s

i

A h i t i s r e c

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d e d w h e n t h e A D C v a l u e g

  • e

s a b

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e p r e

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e fi n e d t h r e s h

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d a n d l a s t s t i l l i t d r

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s b e l

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t h e t h r e s h

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d .

t i me t

s

t

f

t

p

P C S

i

 Wh

a t w e i n t e n d t

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t

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e i n t r i g g e r p r i mi t i v e ?

 -

t s t a r t t i me

 -

t

f

e n d t i me

 -

p e a k t i me

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p e a k a mp l i t u d e

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s u m

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S

i

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e r t h e h i t p e r i

  • d

 I

n t e g r a t e s e v e r a l fi x e d

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i z e w i n d

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s b e f

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e a n d a f t e r p u l s e .

 C

h

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e w h i c h t

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n c l u d e i n c h a r g e e s t i ma t i

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l a t e r

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p t i mi z e s i z e / N u mb e r

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w i n d

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s w i t h s i mu l a t i

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.

Δu t f Δu t Δu t A D C , s

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SLIDE 9

S t a t u s

A mo d i fi e d w r a p p e r ( I / O , b u ff e r i n g e t c . ) i s a l r e a d y p r e s e n t .

V e r s i

  • n

1

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s i mu l a t i

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i s r e a d y ( q u e s t a

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i m)

T h e A l g

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i t h m h a s n

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b e e n s y n t h e s i z e d i n V i v a d

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n d r e a d y f

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r e v i e w a n d f u r t h e r i t e r a t i

  • n

s .

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SLIDE 10

T e s t B e n c h O u t p u t

S i mu l a t i

  • n
  • u

t p u t

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H F A , t e s t e d w i t h a n e x a mp l e w a v e f

  • r

m fi l e c

  • n

s i s t i n g i n c r e a s i n g a d c v a l u e s t

  • i

mi t a t e a c t u a l w a v e f

  • r

m,

H i t s t a r t t i me = 1 5 H i t e n d t i me = 2 5 H i t p e a k = 5 6 7 H i t p e a k t i me = 2 2 H i t s u m = 5 6 3 3 O u t p u t r e a d y = 1

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SLIDE 11

S y n t h e s i s

  • n

V i v a d

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1 7 . 2

S y n t h e s i z e d t h e c

  • d

e

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V i v a d

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1 7 . 2 , t a r g e t b

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r d K C U 1 5

R T L s c h e ma t i c ( e l a b

  • r

a t e d d e s i g n )

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SLIDE 12

U t i l i z a t i

  • n

r e p

  • r

t

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SLIDE 13

R e s

  • u

r c e E s t i ma t i

  • n

I t i s c l e a r f r

  • m

i n i t i a l w

  • r

k t h a t , t h e c u r r e n t a l g

  • r

i t h m t a k e s a v e r y l

  • w

r e s

  • u

r c e s .

F

  • r

9 6 c

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l e c t i

  • n

p l a n e w i r e s a s s u mi n g t h e mu l t i p l e x i n g

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1 i s t

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, t h e L U T ’ s u t i l i z e d w i l l b e , 5 1 4

  • u

t

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2 4 2 4 a v a i l a b l e .

T h i s p

  • r

t u t i l i z a t i

  • n

i s c u r r e n t l y h i g h a s a l l t h e i / p a n d

  • /

p p

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t s a r e i mp l e me n t e d a s 3 2 b i t i n t e g e r ’ s .

I f mu l t i p l e x i n g w e h a v e t

  • a

l s

  • c

h e c k t h e me mo r y u t i l i z a t i

  • n

.

S a v i n g s t a t e b e t w e e n d a t a p a c k e t s n

  • t

y e t i mp l e me n t e d . Wi l l i n c r e a s e me mo r y u s a g e .

N . B . T h e s e a r e v e r y p r i ma r y e s t i ma t e s !

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SLIDE 14

Summary and “To Do”

 Aiming to have end-to-end processing firmware chain in next

month or so.

 Hackton at RAL on 24th Oct

  • Attempt to assemble a chain in hardware

Presenter Name | Presentation Title 14