Statistical Device Variability and Statistical Device Variability - - PowerPoint PPT Presentation

Statistical Device Variability and its Impact on Design

Asen Asenov Device Modelling Group University of Glasgow

Statistical Device Variability and its Impact on Design

Asen Asenov Device Modelling Group University of Glasgow

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

Motivation

• Deterministic variability

Deterministic variability Deterministic variability

• Statistical variability

Statistical variability Statistical variability

• Impact on

Impact on Impact on circuits circuits circuits

• EU variability projects

EU variability projects EU variability projects

• Conclusions

Conclusions Conclusions

The variability is becoming a major headache The variability is becoming a major The variability is becoming a major headache headache

• G. Declerck, Keynote talk, VLSI Technol. Symp. 2005

The local stochastic variability becomes a major source of concern The local stochastic variability becomes a major source of concern

After D. J. Frank, IBM

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

• Motivation

Motivation Motivation

Deterministic variability

• Statistical variability

Statistical variability Statistical variability

• Impact on

Impact on Impact on circuits circuits circuits

• EU variability projects

EU variability projects EU variability projects

• Conclusions

Conclusions Conclusions

OPC and strain related variability

65 nm example Synopsys (SISPAD 06)

OPC and strain related variability

65 nm example Synopsys (SISPAD 06)

Strain induced variability

After W. Fichtner

ECAD tools can deal reasonably well With deterministic variability

Restricted design rules and uniformity Restricted design rules and uniformity

After H. Onodera

• Irregular gate-poly

pitch

• Horizontal poly

wires

• Constant pitch with

dummy poly insertions

• Dummy poly

patterns

• Stretched gate-poly

extensions

• Constant pitch with

dummy poly insertions

• Stretched gate-poly

extensions

• Single orientation

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

• Motivation

Motivation Motivation

• Deterministic variability

Deterministic variability Deterministic variability

Statistical variability

• Impact on

Impact on Impact on circuits circuits circuits

• EU variability projects

EU variability projects EU variability projects

• Conclusions

Conclusions Conclusions

Statistical variability Statistical variability

The simulation Paradigm now A 22 nm MOSFET In production 2008 A 4.2 nm MOSFET In production 2023

Random discrete Random discrete dopants dopants

Continuous process simulation Synopsys Atomistic process simulation

• M. Jaraiz

KMC Simulator

Line edge roughness (LER) Line edge roughness (LER)

Sandia Labs – EUV

1D Fourier synthesis

Poly silicon grain boundaries Poly silicon grain boundaries

Poly Si grains, SEM Interdigitised

High High-

• κ

κ morphology morphology

κ1 κSiO2 κ2 κSiO2 κ1 α α H(x) x

HfSiO HfO2

Measured and simulated variability Measured and simulated variability

LP LP MOSFETs MOSFETs 45nm technology node 45nm technology node

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1E-11 1E-9 1E-7 1E-5 1E-3

Vgs (V)

Results from Crolles 2 Results from Atomistic Simulator

N-Channel 42 nm gate length

VT (50 mV) VT (1.1 V) Experiment 62 mV 69 mV Simulation 62 mV 67 mV

Combined variability in Combined variability in bulk bulk MOSFETs MOSFETs

35nm 25nm 18nm 13nm 9nm

Measured

TI IBM Fuj Int

LER follows ITRS LER=4nm

The true shape of the distribution The true shape of the distribution

Based on the simulation of 100000 transistors Based on the simulation of 100000 transistors

MOSFET capacitance variability MOSFET capacitance variability

Gate capacitance Drain capacitance

Interconnect variability Interconnect variability

After: T. D. Drysdale

45 nm 32 nm 22 nm

delay (p.u.l)

LER=5nm

45 nm 32 nm 22 nm

delay (p.u.l)

LER follows ITRS

45 nm 32 nm 22 nm 45 nm 32 nm 22 nm no improvement improvement

Gate tunnelling leakage variability Gate tunnelling leakage variability

Interface pattern Electron distribution Current density

Statistical reliability Statistical reliability

Continuous Single trap Multiple traps

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

• Motivation

Motivation Motivation

• Deterministic variability

Deterministic variability Deterministic variability

• Statistical variability

Statistical variability Statistical variability

Impact on circuits

• EU variability projects

EU variability projects EU variability projects

• Conclusions

Conclusions Conclusions

Deterministic vs. statistic variability Deterministic vs. statistic variability

2 billion transistors: VT1=200mV VT2=300mV

0.E+ 00 5.E+ 07 1.E+ 08 2.E+ 08 2.E+ 08 3.E+ 08 0.2 0.4 0.6 0.8 0.E+ 00 1.E+ 07 2.E+ 07 3.E+ 07 4.E+ 07 5.E+ 07 6.E+ 07 0.2 0.4 0.6 0.8 0.E+ 00 1.E+ 07 2.E+ 07 3.E+ 07 4.E+ 07 0.2 0.4 0.6 0.8 1.E+ 00 1.E+ 01 1.E+ 02 1.E+ 03 1.E+ 04 1.E+ 05 1.E+ 06 1.E+ 07 1.E+ 08 1.E+ 09 0.2 0.4 0.6 0.8 1.E+ 00 1.E+ 01 1.E+ 02 1.E+ 03 1.E+ 04 1.E+ 05 1.E+ 06 1.E+ 07 1.E+ 08 0.2 0.4 0.6 0.8 1.E+ 00 1.E+ 01 1.E+ 02 1.E+ 03 1.E+ 04 1.E+ 05 1.E+ 06 1.E+ 07 1.E+ 08 0.2 0.4 0.6 0.8

VG [V]

σVT=10mV σVT=50mV σVT=100mV

Compact model strategies

5 10 15 20 25 30 10 20 30

Frequency Relative error (%) With parameter rdswmin, nfactor, voff, a1, a2 and d

5 10 15 20 25 30 10 20 30

Frequency Relative error (%) With parameter vth0

5 10 15 20 25 30 10 20 30

Frequency Relative error (%) With parameter vth0, voff

5 10 15 20 25 30 10 20 30

Frequency Relative error (%) With parameter vth0, voff and rdswmin

5 10 15 20 25 10 20 30

Frequency Relative error (%)

with 1-parameter set with 2-parameter set with 3-parameter set

0.0 0.4 0.8 Vd (Vo lts)

L ine s: BSI M3v3 Symbo ls: Data

Vgs=0.85V Vgs=0.75V Vgs=0.65V Vgs=0.55V Vgs=0.45V Vgs=0.35V

BSIM

Impact of bulk MOSFET scaling of SRAM Impact of bulk MOSFET scaling of SRAM

2 3 4 80 120 160 10 20 30

SNM Mean Value (mV) Cell ratio

13nm, Mean Value 18nm, Mean Value 25nm, Mean Value SNM SD (mV) 13nm, SD 18nm, SD 25nm, SD

80 120 160

<SNM> [mV] σSNM [mV]

0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0

Vout2(V) V

• ut1(V)

Vout1 [V] Vout2 [V]

Hard logic faults Hard logic faults

0.0 0.2 0.4 0.6 0.8 1.0 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4 VG [V] ID [A] 0.0 0.2 0.4 0.6 0.8 1.0 1e-9 1e-8 1e-7 1e-6 1e-5 1e-4 Vin [V] Vout [V]

L/W=18/18nm

Timing variability Timing variability

20 30 40 50 60 70 10 20 30

Frequency Delay (ps)

CMOS NAND CPL NAND DPL NAND DOMINO NAND DDCVS NAND

Time [s] Voltage [V]

Performance/Power/Yield (PPY) trade Performance/Power/Yield (PPY) trade-

• off
• ff

Power Performance

95 75 35 5

Yield, % Power Performance

35 5

Yield, %

95 75

90nm TG 45nm TG

Performance Energy

Pareto optimal curve (M. Horowiz, IEDM05)

The monitors and knobs approach The monitors and knobs approach

The “Technology Aware Design” of IMEC

The Power 6 processor of IBM The Power 6 processor of IBM

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

• Motivation

Motivation Motivation

• Deterministic variability

Deterministic variability Deterministic variability

• Statistical variability

Statistical variability Statistical variability

• Impact on

Impact on Impact on circuits circuits circuits

EU variability projects

• Conclusions

Conclusions Conclusions

Meeting the Design Challenges of Nano- CMOS Electronics - eScience Pilot Project Meeting the Design Challenges of Nano- CMOS Electronics - eScience Pilot Project

University Partners Edinburgh University MMDGUE, NeSCE Glasgow University DMGUG, MSTGUG, NeSCG Manchester University APTGUM, eSNW Southampton University ESDGUS York University ISGUY Industrial Partners Synopsys, ARM, Wolfson Microelectronics, Freescale, National Semiconductors, Fujitsu, NMI Resources £3.3M EPSRC, £4.1M FEC, £5.3M IC 11 PDRAs 7 Science4 e-Sci 7 PhD

Grid based statistical simulation Grid based statistical simulation

CMOS variability research in Europe ESSDERC/ESSIRC 2008 Workshop CMOS variability research in Europe ESSDERC/ESSIRC 2008 Workshop

NANOSIL: Silicon-based nanostructures and nanodevices for long term nanoelectronics applications (EU FP7), R. Clerc PULLNANO: Pulling the limits of the nano CMOS Electronics (EU FP6), H. Maes REALITY: Reliable and variability tolerant system on a chip design in More-Moore technologies (EU FP7)

• B. Dierickx, IMEC

NanoCMOS: Meeting the design challenges of the nano-CMOS electronics (UK EPSRC), A. Asenov, GU NanoMat: Meeting the material challenges of the nano CMOS electronics (UK EPSRC), A. Shluger, UCL

Summary

Motivation Deterministic variability Statistical variability Impact on circuits EU variability projects Conclusions

Summary Summary

• Motivation

Motivation Motivation

• Deterministic variability

Deterministic variability Deterministic variability

• Statistical variability

Statistical variability Statistical variability

• Impact on

Impact on Impact on circuits circuits circuits

• EU variability projects

EU variability projects EU variability projects

Conclusions

Conclusions Conclusions

The statistical variability will be increasing in the

next technology nodes.

The statistical variability can not be reduced by

fine tuning the technology, OPC and regular designs.

The statistical variability demands statistical

approach to design and will force fundamental design changes.

The fabless and the chipless companies have to

learn more about technology and devices.

Acknowledgements to all members of the Device Modelling Group Acknowledgements to all members of the Device Modelling Group

Department of Electronics and Electrical Engineering University of Glasgow