[PPT] - Solutions Patrice Joubert Doriol 1 , Aurora Sanna 1 , Akhilesh PowerPoint Presentation

SLIDE 1

SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

Patrice Joubert Doriol1, Aurora Sanna1, Akhilesh Chandra2, Cristiano Forzan1, and Davide Pandini1

1STMicroelectronics, Central CAD and Solutions, Agrate Brianza, Italy 2STMicroelectronics, Central CAD and Solutions, Greater Noida, India

IBIS Summit, May 16th, 2012, Sorrento, ITALY

SLIDE 2

Today’s I/Os Challenges

Higher I/O account
Increasing operating frequencies
Faster signal edge rates
High I/O density makes it difficult to place PCB decaps close enough

to the pads

Automotive specific challenge: I/Os signal conducted EMI
EMC and signal integrity are another mandatory objective for first

silicon success

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 3

EMC At The End Of The Design Flow

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CMOSM10 Full Mask Set Back-End Metal Fix 6ML $640K $340K 4ML $460K $200K CMOSM55 Expected mask set cost aligned with CMOSM10

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 4

Our Vision: EMC-Aware Design

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DESIGN FABRICATION

EMC compliant EMC Design Guidelines EMC Tools EMC Training Architectural Design Floorplan Synthesis and Place&Route Verification

EMC Simulations Compliance?

YES NO

EMC Models

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 5

Reflection, Crosstalk, And SSO Noise

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Trace 1 Trace 2 Trace3 Victim Chip 2 Chip 1

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 6

SSO Noise And Conducted EMI

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V = L·dI/dt I/O signal noise I/O signal conducted emissions VDD Switching aggressor VDD Stable victim Stray capacitance Ground inductance Discharge current

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 7

I/O Ring Circuit

Any realistic signal integrity and EMI simulation must include the

complete system-level macromodel (die, package, board)

A full transistor-level simulation of the I/O ring is impractical even for a

limited number of adjacent toggling I/Os and a given victim

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 8

SSO Flow

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 9

SSO Analysis For Automotive Applications

STYY: Microcontroller in CMOSM10-

4ML

Size: 4.1x4.1 = 16.81mm2
Instances: 365K
Main Clock: 64MHz
Package: LQFP144 (Wire bonding)

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 10

STYY I/O Bank For EMI Analysis

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PAD_107

BD2S3MS1ARUD_FC_ISO

PAD_106

BD2SS1RUD_FC_ISO

PAD_35

BD2SS1RUD_FC_ISO

PAD_78

BD2SS1RUD_FC_ISO

PAD_34

BD2S3MS1ARUD_FC_ISO

PAD_79

BD2S3MS1ARUD_FC_ISO

PAD_5

BD2S3MS1ARUD_FC_ISO

PAD_111

BD2S3MS1ARUD_FC_ISO

PAD_6

BD2SS1RUD_FC_ISO

PAD_33

BD3M10FS1ARUDLP_FC_ISO

VSS_HV_IO0_N0

VSSIO_ESDHV_FC_ISO

VSS_HV_FLA0

VSSCO_FC_ISO

VDD_HV_FLA0

VDDCO_FC_ISO

VDD_HV_IO0_N0

VDDIO_FC_ISO

PAD_TMS

BD2S3MS1ARUD_FC_ISO

M S S S S M M M M M F

VSS (0V) VDD (5V)

PG15 PE14 PE15 PG10 PC3 PC2 PA5 PA6 TMS PC1 PG11

PG[11]

Conducted Emission Test Pin Stable Victim

Switching aggressors

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 11

Design Solutions For SSO Noise Reduction

I/Os’ signal skewing
I/O ring fillercap insertion
I/O pads reduced driving strength
I/O ring power/ground supply placement

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 12

I/O Skewing Impact on EMI

Typical I/Os’ working frequency for automotive applications are in the

range of a few KHz and do not need to toggle synchronously

A relative skew in the range of about 10ns is compatible with a correct functionality
f the I/O ring
Harmonic amplitude reduction of several dBµVs obtained in the

frequency range of 1GHz

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On some critical harmonics amplitude reduction of about 10dBµV

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 13

I/O Fillercaps Insertion And Driving Strength Reduction

I/O fillercap insertion did not prove to be an effective technique
Huge amount of decaps and related area to achieve only few dBµV amplitude

reduction

Difficult to exploit this technique on typical pad-limited I/O rings
I/O driving strength reduction (when compliant with the timing

constraints) from MEDIUM to SLOW strength version can further reduce the SSO noise

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 14

SSO Flow Validation

The gate-level SSO flow was validated vs. full Spice-level simulations

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Victim PAD Output Aggr. PADs Input

40.93 20.13

SSO_AMF

39.06

2nd Peak (mV)

19.74

SPICE 1st Peak (mV)

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 15

IBIS For SSO And EMI Analysis

Traditionally IBIS models have been used for signal integrity

simulations on system PCBs

Behavioral modeling
IP protection
Fast simulation time
Reasonable accuracy
However IBIS v4.0 cannot include predriver and crossbar currents

and I/O ring power/ground supply bouncing which is the dominant source of SSO and conducted EMI

To validate IBIS v5.0 for EMI analysis the same STYY I/O bank was

used

IBIS v5.0 was compared vs. full transistor-level simulations

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 16

IBIS Validation Flow

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Board model power and signal traces SPICE Package model I/Os Spice netlist

Time- domain waveforms

Frequency-domain analysis

SSO Spectra Conducted EMI

I/Os IBIS model

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 17

IBIS For SSO And EMI Analysis

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IBIS v5.0 vs. Spice

Time-domain analysis Frequency-domain analysis

IBIS vs. Spice: good accuracy up to 2GHz

IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions

SLIDE 18

Summary

CAD flow and design solutions for SSO and I/O conducted EMI

analysis and optimization were presented

Methodology exploited on an industrial automotive microcontroller in

ST 90nm with eNVM technology

IBIS v5.0 can be used for a reliable SSO and EMI analysis

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08/05/2012 IBIS Summit 2012 – SSO Noise And Conducted EMI: Modeling, Analysis, And Design Solutions