SLIM: Short Cycle Time and Low Inventory in Manufacturing at - - PowerPoint PPT Presentation

8/10/2020 SLIM Presentation 1

SLIM: Short Cycle Time and Low Inventory in Manufacturing at Samsung Electronics Corp., (SEC)

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Introductions

• Prof. Rob Leachman, UCB IEOR Dept., technical

author and SLIM project manager

• Dr. Jeenyoung Kang, Leachman & Associates LLC,

technical author (UCB IEOR PhD ‘96)

• Dr. Vincent Lin, Leachman & Associates LLC,

technical author (UCB IEOR PhD ‘99)

• Mr. J. W. Kim, SEC Executive VP Semiconductor

Manufacturing, SLIM project sponsor

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Introduction to SEC

• Market share leader in DRAMs, SRAMs,

TFT-LCDs

• Design and fabrication of integrated circuits

centered in Kiheung, Korea

– 11 large fab lines, 20,000 employees – 500,000 wafers per month

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SEC in Kiheung, Korea

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The business problem

• 1995: DRAM manufacturers enjoy record

profits

• At end of 1995, DRAM market changed

from seller’s market to buyer’s market

• Urgent need to reduce manufacturing cycle

time

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The business problem

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The project

• SLIM project initiated in March, 1996
• Ground rules:

– joint effort of SEC and outside IE/OR experts – cycle time reduction as early as possible – consensus approval and credibility of solutions – no diminution of yields or productivity

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Some fab terminology

• Cycle time (a.k.a. lead time or flow time)
• WIP (work-in-process)
• Fab-out schedule
• Steppers (photolithography machines,

usually the fab bottleneck)

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The challenge

Fabrication of advanced memory devices

• Re-entrant manufacturing process
• Fragile manufacturing process

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The challenge (cont.)

Device Step Qualified Steppers XC 1.0 #2, #5, #68 ZB 1.0 #1, #2, #5 UC 1.0 #8, #9 SB 1.0 #1 XC 5.0 #61, #65, #86

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SLIM scheduling principles

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Conventional paradigm: lot-based dispatching

• Scheduling objects: lots
• Paradigm: when machine is idle, select suitable lot

with the highest priority

• Determine efficient priority rules

– Most commonly, priority is given to lots determined to be behind schedule

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Problems with conventional lot dispatching

A-1 B-1 A-2 B-0 A-1 B-1 Machine M1 Machine M2 Start of shift

Note: “A-1” denotes a lot of device A with a slack score = 1.

Time Lot dispatching systems schedule too many changeovers.

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More problems with lot dispatching

Cycle time to fab out A-1 A-4 A-3 A-2 B-3 B-2 B-1 3 2 1

Note: “A-1” denotes a lot of device A with slack = 1

A-1 is the wrong choice! Lot due dates become stale because

• f lots passing one another, changes to the fab out schedule,

and downstream yield losses.

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SLIM paradigm: manage WIP

• Scheduling objects: device/steps
• Paradigm: determine how many lots of each step of

each device should be completed this shift, and allocate to machines intelligently

• Maintain target WIP profile, maximize bottleneck

throughput, and control frequency of recipe changes

• Schedule non-production work, not just production

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SLIM schedules

A-1 A-1 A-2 B-0 B-1 B-1 Machine M1 Machine M2 Start of shift Time

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Fab out schedule

SLIM works to a target fab out schedule

• Expressed through continuous-time for every

device

• Analyzed to be capacity-feasible and consistent

with the WIP

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Target cycle time

• The target cycle time for each device is established

according to standard learning curves:

1 1.5 2 2.5 1 2 3 4 5 6 7 8 9 10

Months since qualification Cycle time / mature cycle time Similar technology Different Very different

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Target cycle time for steps

• The process time plus material handling time for each

step is termed the standard cycle time (sct).

• The difference between the target cycle time and the

total standard cycle time for a device is its total buffer time (TBT).

• A key strategy of SLIM concerns how one allocates

TBT among steps of the process flow...

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Allocating buffer time

WIP profile when there is no process or equipment trouble: Photo Layer 1 Photo Layer 2 Photo Layer 3 Photo Layer 4

Fab process

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Allocating buffer time

Photo Layer 1 Photo Layer 2 Photo Layer 3 Photo Layer 4

Fab process

Process trouble WIP profile when there is process trouble: Layer 3 photo WIP running out

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Target cycle time for steps

• SLIM allocates TBT to steps according to statistics
• n actual cycle time.
• Non-bottleneck steps are not allocated buffer time.
• Bottleneck steps are allocated buffer time in

proportion to the discrepancy between the upstream actual cycle time and the standard cycle time ...

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Target cycle time for steps

where ,

ij ij ij

bt sct tct + =

, device

• n

step bottleneck For i j

( )

( )

i NB j ij ij ij ij ij

TBT SCT ACT SCT ACT bt

i

∑

=

− − =

1

. and 1 steps bottleneck between time cycle standard total the is and time cycle actual average the is CT and j j SCT A

ij ij

−

Target cycle time for steps (cont.)

• Alternatively, if we have data on the standard

deviation of layer cycle times, we could use that data to set target buffer times:

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( )

i NB j ij ij ij

TBT bt

i

∑

=

=

1

σ σ

. product

• n

and 1 steps bottleneck between time cycle actual

• f

deviation standard the is and i j j

ij

− σ

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Target cycle time proposed by others

• Use a common multiple of theoretical cycle time, or
• Set target proportional to actual or simulated average cycle

time

• Targets set this way average over events when the WIP is

dislocated from where it is needed. They do not try to concentrate as much WIP in front of bottleneck steps downstream from trouble spots as does SLIM, and consequently they require more WIP to achieve a target level of utilization.

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Ideal production quantity

1 2 3 4 5 6 7 8 9 Fab out schedule Target cycle time to fab out

• IPQ of a device/step = how many units need to be

completed by the end of the shift to meet the target cycle time and the target fab outs

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Ideal production quantity

• IPQ = (Target fab outs due until the target cycle time

to fab out plus one shift)

• (actual fab outs to date)
• (actual downstream WIP)

1 2 3 4 5 6 7 8 9 Fab out schedule Target cycle time to fab out

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Ideal production quantity

( )( )

        − −         =

∑ ∫ ∫

+ = + ∞ − ∞ − ik N j k ik TCTFO i i ij ij

AW FY dt t AFO dt t TFO FY IPQ

i ij

1 33 .

) ( ) ( 1

• IPQ = (Target fab outs due until the target cycle time

to fab out plus one shift) - (actual fab outs to date)

• (actual downstream WIP)

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Schedule score

• SS of device/step = how many days early or late is

the current production of this device/step

• SS = - IPQ / (Avg. fab out rate over cycle time to out)
• SLIM prioritizes device/steps by SS, and strives to

complete the IPQ for each device/step

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SS vs. Least slack (“Delta days”)

FAB 6: U27YJ

1.05 1.75 1.20 1.00 2.10 1.15 1.44 2.93 2.86 1.18 1.59 1.92 1.04 1.71 1.21 2.45 1.08 3.23 1.05 1.03 10.00

100 200 300 400 500 600 700 800 900

Wafers

• 10
• 8
• 6
• 4
• 2

2 4 6 8 10

Days

3750 3824 3348 3471 3752 3677 3015 3459 4278 3889 3823 4019 3814 3615 4096 3769 3242 3814 1895 1475 Wafers w/in MTTS week Wafers DUE in week

• .53 Mean Delta .8583 Mean CR

35013 Total Wafers 08/11/06 09:06 AM - Inventory current as of 08/11/06 07:48 AM

Base: FAB 6 U27YJ Inc.: FAB 6 U27YJ RWK: Yes HOLD: Yes HOT: Yes RUN: Yes Max MTAS : 10 WIP Labels: > 150 Start: End: Lot # Filter: LIKE '*' PC Filter: LIKE '*' PC Rt. Filter: LIKE '*'

• Trav. Filter: LIKE '*'

Part Filter: LIKE '*'

• Des. Filter: LIKE '*'
• Ven. Filter: LIKE '*'

Cycle Time-66 Line Yield-97%

Scheduling Score Delta

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Balance index

According to BI, step B should be dispatched first

Step B Next photo step

Downstream WIP situation:

Step A Next photo step

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Balance index

• BI of non-bottleneck step = score indicating relative

surplus or deficit of actual WIP vs. target WIP downstream up to next bottleneck step: BI = (AW – TW)/TW where AW is the actual WIP summed over all steps up to the next bottleneck step and TW is the target WIP up to the next bottleneck step

• SLIM also considers BI in addition to SS when

prioritizing device/steps.

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Photo Diffusion Thin Films Etch Fab In Fab Out SLIM - S

• Schedule scanners

so as to complete IPQs and for maximum utilization

SLIM - I

• Control fab-ins

according to target WIP levels and stepper capacity

SLIM - D

• Form batches
• f device/steps with

low SS and low BI WIP

SLIM – E,T

• Schedule

device/steps with low SS and low BI

SLIM scheduling

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SLIM logic

• Make a shift schedule, with on-line updates
• Prioritize device/steps by SS and BI
• First pass: Assign WIP to complete IPQs by

end of shift

– Choose machine based on setup avoidance, least candidate WIP, etc.

• Second pass: Assign remaining WIP

– Save changeovers where possible

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SLIM-S schedule

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SLIM planning

• A sophisticated linear programming model

(“SLIM-O”) is utilized to identify specific bottlenecks for fab-out demands

• SLIM-O is utilized to plan the ramp-up of new

devices (“capacity simulation”)

– how many machines to install and when – which machine/steps to qualify when

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SLIM planning

SLIM-O models the inter-step arrangement constraints:

Step Qualified machines

1.0 #04 #37 #39 5.0 #44, #46 #44, #45 #01, #03 9.0 #44, #46, #57 #44, #45, #57 #01, #03, #57

SLIM-O optimizes the routing of WIP through the machines

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Key ideas of SLIM

• We can reduce total WIP and cycle time by wisely

positioning the buffer WIP

– Concentrate buffer WIP at the bottleneck steps following the troublesome portions of the process flow – Then we can lower the overall factory WIP and still achieve the same fab throughput

• Good scheduling can increase area throughput for the

same level of WIP

– Then we can lower overall WIP some more

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SLIM implementation

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SLIM teams

• SLIM project teams for pairs of fab lines

– First team formed in March, 1996 for Lines 4 and 5 – Team for Lines 6 and 7 started March, 1997 – Ultimately, 8 SLIM teams were formed

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SLIM steering committee

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SLIM teamwork

• Inter-disciplinary team membership

– including several with graduate OR/MS training

• Developed SLIM database and SLIM modules
• Trained 3,000 people in SLIM logic & use

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SLIM training

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SLIM results

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SEC DRAM cycle times

20 30 40 50 60 70 80 90 100

Dec-95 Jun-96 Dec-96 Jun-97 Dec-97 Jun-98 Dec-98 Jun-99

• Avg. fab cycle time (days)

4M 16M 64M 128M

SLIM begins SLIM begins Standard cycle time SLIM begins

• n all lines

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Benefits of SLIM

• Faster rate of yield improvement
• Reduction of late production deliveries

Before After At Die out 30% 4% At Test out 26% 3%

• Reduced lead times to customers
• Higher selling prices ...

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Financial impact of SLIM

• Sales revenues for the DRAM output of the

Kiheung fab lines March, 1996 - December 2000 were tallied: $21.9 billion

• Sales revenues were re-computed assuming

fab cycle times had stayed at 80 days

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DRAM selling prices

0.00 20.00 40.00 60.00 80.00 100.00 120.00 140.00 160.00 180.00 200.00 Mar-96 Sep-96 Mar-97 Sep-97 Mar-98 Sep-98 Mar-99 Sep-99

Average selling price ($)

4M 16M 64M 128M

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Financial impact of SLIM

• The result: SLIM increased DRAM sales

revenues by US $954 million

– Including non-DRAM production, the revenue gain was $1.1 billion just during the project, billions more in subsequent years

• Market share up from 18% to 22%, later up

to 34%

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Competitive impact of SLIM

• Japanese companies retrench from DRAM

market, IBM and TI exit market

• Hynix effectively bankrupted, Micron and

Infineon suffer heavy losses

• SEC becomes most profitable

semiconductor manufacturer

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Adoption of Methodology

• SLIM ported to SEC’s LCD factories
• After publication, SLIM methodology

increasingly adopted by other semiconductor manufacturers and influencing commercial software vendor

• fferings and customer choices

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Summary of SLIM

• Target cycle time methodology
• On-line scheduling
• Simulation
• Advanced LP planning
• Trained 3,000 people

Number one in DRAMs!