Signal Integrity Simulation and Equivalent Circuit Modeling - - PowerPoint PPT Presentation
NTU Signal Integrity Simulation and Equivalent Circuit Modeling Tzong-Lin Wu Department of Electrical Engineering National Taiwan University Taipei, Taiwan wtl@cc.ee.ntu.edu.tw Outline NTU Introduction Signal Integrity Simulation in
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Tzong-Lin Wu Department of Electrical Engineering National Taiwan University Taipei, Taiwan wtl@cc.ee.ntu.edu.tw
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Introduction Signal Integrity Simulation in SPICE
A case Study: Driver Board of TFT Display Panel
TDR Concept and Layer Peeling Technique (one port) Macro-model Synthesis for Coupled Discontinuities
Challenge of SI Modeling for Real PCB and Package Summary
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With rapidly increased clock rate and denser interconnect layout, noise caused by the discontinuities can be a critical factor to degrade the signal integrity (SI) of circuit systems. Example: Via coupling
step
V
TDT
V
Coupling
2E-011 4E-011 6E-011 8E-011 1E-010 1.2E-010
t (s)
0.005 0.01 0.015 0.02 0.025
V T D T ( v
t )
Signal rising time 100ps 50ps 20ps 10ps
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GND Power
Extracting SPICE-compatible models for those discontinuities are essential. Benefits:
under SPICE environment.
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Case Study: Driver Board of TFT Display
Time Controller (T-CON) Driver IC
Driver PCB
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Objectives of this project:
Signal integrity modeling for the driver PCB and compare with the measured results.
Approaches:
Establishing SPICE-compatible model for all interconnects and doing SI simulation on HSPICE.
IC I/O Buffer Model
SPICE model IBIS model
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TCON
Driver IC Driver IC Driver IC
via1 via2 via3 via3
Differential line (no GND) Differential line (with GND)
FPC FPC FPC
Step 1: Trace all interconnects from driver (T-CON) to receiver (driver IC)
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GND
Differential line (with GND) Differential line (no GND)
Step 2: Extract SPICE Compatible models for each partitioned interconnects by Ansoft Q3D (Differential signals)
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TCON
Driver IC Driver IC Driver IC
Differential line (no GND) Differential line (with GND)
via1 via2 via3 via3 FPC FPC FPC
via1. via2.
Step 2: Extract SPICE Compatible models for each partitioned interconnects by Ansoft Q3D (Differential Via Holes)
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2 1 3 4
via1.
1 2 3 4 Via Macro-model (type 1)
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via2.
Via Macro-model (type 2)
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TCON
Driver IC Driver IC Driver IC
via1 via2 via3 via3
Differential line (no GND) Differential line (with GND)
FPC FPC FPC
Step 2: Extract SPICE Compatible models for each partitioned interconnects by Ansoft Q3D (Flexible PCB)
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Substrate : polyimide Differential line
3.5)
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TCON
Differential line (no GND) Differential line (with GND)
軟板 軟板 via1 via2 via3 via3 TCON (IBIS . spice)
Case1 : Open circuit for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON) Measuring Probes 軟板
via2 軟板
100Ω
Step 4: Comparison between modeling and measurement
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0.05 0.1 0.15 0.2 Spice IBIS measurement
Case1 : Open circuit for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)
Step 4: Comparison between modeling and measurement
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TCON
Driver IC
Differential line (no GND) Differential line (with GND)
軟板 軟板 via1 via2 via3 via3 TCON (IBIS . spice) Driver (IBIS) 訊號觀測點
Driver IC
軟板 Driver (IBIS) via2 軟板 Driver (IBIS)
100Ω
Driver (IBIS)
Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)
Step 4: Comparison between modeling and measurement
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Case2 : Using IBIS model for the receiver side (Driver IC) Using SPICE and IBIS models for transmitted side (T-CON)
Step 4: Comparison between modeling and measurement
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Introduction Signal Integrity Simulation in SPICE
A case Study: Driver Board of TFT Display Panel
TDR Concept and Layer Peeling Technique (one port) Macro-model Synthesis for Coupled Discontinuities
Challenge of SI Modeling for Real PCB and Package Summary
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2 d cable t
load circuit
short circuit
step
V
2
step
V
1 Γ = Γ =
1 Γ = −
Coaxial cable
TDR
V
step
V
r
st T e DR p r
V V V = +
Time-Domain Reflectometry (TDR)
(1 )
TDR step r step
V V V V = + = + Γ ⋅
/
L L
Z Z Z Z Γ = − +
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Z Z Z Z
C
L
step
V
capacitive dip
step
V
inductive peak
Coaxial cable
TDR
V
step
V
r
st T e DR p r
V V V = +
Time-Domain Reflectometry (TDR)
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1
x
1
Z
d
T
1,j
a−
1, j
b−
( )
I t
2
x
2
Z
d
T
3
x
d
T
i
x
i
Z
d
T
, i j
a−
, i j
b−
, i j
b +
, i j
a+
, 1 i j
b
+
+
, 1 i j
a
+
+
( )
V t
Z
2
Z
1
Z
1
X
2
X
3
X
X ← Δ →
1 i
Z + 1 i
x +
( )
in
V t
s
Z
,1 1 1 ,1 i i i i i i i
− − − −
1 , , 2 2 , ,
i j i j i i i i j i j
+ − − + −
1, , 1, , 1 i j i j i j i j
− + + − + + +
1 1
1 1
i i i i i i i i i i i i
Z a b Z a b a b a b Z Z
− − + + − − − + + −
+ = + − = −
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Begin
i=N? i=i+1 End
1
1 1
i i i i
Z Z − + Γ = − Γ
( )
1 , , 2 2 , ,
1 1 1
i j i j i i i i j i j
a a b b
+ − − + −
⎡ ⎤ ⎡ ⎤ − Γ ⎡ ⎤ = − Γ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ − Γ ⎣ ⎦ ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦
,1 ,1 i i i
b a
− −
Γ =
TDR in
V V ⇒
1, 1 1, 1 j j
a a b b
− − − −
= = 50, 1 Z i = =
1, , i j i j
a a
− + +
=
1, , 1 i j i j
b b
− + + +
= 1,2,3, , j N i = −
, j N i = −
x
1
Z
d
T
1,j
a−
1, j
b−
( )
I t
2
x
2
Z
d
T
3
x
d
T
i
x
i
Z
d
T
, i j
a−
, i j
b−
, i j
b +
, i j
a+
, 1 i j
b
+
+
, 1 i j
a
+
+
( )
V t
Z
2
Z
1
Z
1X
2X
3X
X ← Δ →
1 iZ + 1 i
x +
( )
in
V t
s
Z
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TDR
V
1 2 3 4 5 6 7
t (ns)
0.05 0.1 0.15 0.2 0.25 0.3
VTDR (volt)
1 2 3 4 5 6 7
t (ns)
20 30 40 50 60 70 80 90 100 110
L i n e I m p e d a n c e ( O h m )
70 ohm 100 ohm 40 ohm 50 ohm
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Introduction Signal Integrity Simulation in SPICE
A case Study: Driver Board of TFT Display Panel
TDR Concept and Layer Peeling Technique (one port) Macro-model Synthesis for Coupled Discontinuities
Challenge of SI Modeling for Real PCB and Package Summary
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IC
IC
Through-hole via
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L
R
1
M
2
M
3
M
Port 1 Port 2
L
R Z =
Z Z
step
V
Terminatted traces Anti-Pad
Via-Pad
trace1 trace2 trace3
trace4 TDR
TDR
TDT
TDT
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: incident wave : reflected wave :stimulative port : detected port :step response
mn
a b n m
i m mn i n
1
mn
i i mn mn mn
L i
=
: residues : poles : mode numbers
i mn i mn mn
L
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11 22 12 21 11 22 12 21 21 21 11 22 12 21 11 22 12 21 21 21
(1 )(1 ) (1 )(1 ) 2 2 1 (1 )(1 ) (1 )(1 ) 2 2 Z A B C D Z ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ + − + + + − ⎡ ⎤ ⎢ ⎥ ⎡ ⎤ ⎢ ⎥ = ⎢ ⎥ − − − − + + ⎢ ⎥ ⎣ ⎦ ⎢ ⎥ ⎣ ⎦
1 2 3
1 1 1 D A M M M B B B − − ⎡ ⎤ = ⎢ ⎥ ⎣ ⎦
( ) ( )( ) ( )( ) ( ) ( )( ) ( )( ) ( ) ( )( )
11 22 12 21 21 1 11 22 12 21 11 22 12 21 21 2 11 22 12 21 21 3 11 22 12 21
(1 )(1 ) 2 1 (1 )(1 ) (1 )(1 ) 2 1 (1 )(1 ) 1 2 (1 )(1 ) M s Z M s Z M s Z ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ − + + − + + − + − + − + + − = + + −
= =
Lapalace transformation:
1
mn
L i mn mn i i mn
=
Impulse response:
L
R
L
R
1
M
2
M
3
M
Port 1 Port 2
Z Z
1 1
* 1 1 1 1 1 1 1 1 1
( ) ( ) ( )
i i i
N i N i N i k k k i i i i i i i k k k k k k k k
r r r M s s K s s j s j
α α β α β
= = =
+ + + + + −
1
mn
L i mn mn i i mn
r y s s p
=
= +
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1 1
* 1 1 1 1 1 1 1 1 1
( ) ( ) ( )
i i i
N i N i N i k k k i i i i i i i k k k k k k k k
r r r M s s K s s j s j
α α β α β
= = =
+ + + + + −
1 1 1 1
1 1 1 1 1 * 1 1 1 1
( ) ( ) ( )
i i i i k k i i k
N i N i k k i i i i k k k k k r D r D N i k i i i k k k r D
r r M s s s s j r K s j
α α β α β
= = ≥ ≥ = ≥
+ + + + −
We define a parameter D for mode selection
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* *
1
M
2
M
3
M
12
Y −
11 12
Y Y +
22 12
Y Y +
1 3 3 11 12 3 2 3 21 22
11 1 3 12 21 3 22 2 3
1 3 3 3 2 3
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1
2 1 1
i i
K K i i i i i i i i i i q v
= = > >
1 1 1 1
* 1 1 1 1 1 1 1 1 1
( ) ( ) ( )
i i i i i i k k k
N i N i N i k k k i i i i i i i k k k k k k k k r D r D r D
r r r M s s K s s j s j
α α β α β
= = = ≥ ≥ ≥
+ + + + −
2 3
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1
2 1 1
i i
K K i i i i q v i i i i i i
= = > >
1
Ci Ci i
R Y s s R C = +
1 1
Ci i Ci i i
R C q h R = =
i
C
i
C
R
i
C
i
C
R
i
L
R
i
L
1 1
i Ci i Li Ci i Li i i i i i i i i i
v m r u v C R C R R R L r r C m = ⎛ ⎞ = − ⎜ ⎟ ⎝ ⎠ = − ⋅ = ⋅
2(
) ( )
i i i i i i
i i i L L i i C i i C L i i L
sLC C R Y s s R LC R LC s R R C L R + = + + + +
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3 2
2 1 1
i i
i i i K K i i i q v i i i
= = < <
i
C
2 ( )
i
C
V s
( )
i
C
V s + −
i
C
R
i
C
R
2 ( )
i
L
V s
L
i
L
R
i
C ( )
i
C
V s + −
2 ( )
i
C
V s
( )
i
L
V s + −
1 1
Ci i i i Ci
R q C h R = − = 1 1
i i Li Ci i i i Li i Ci i i i i i i
v C R R m r r R r R u L v C C m − = = − ⎛ ⎞ ⋅ = + = ⎜ ⎟ ⋅ ⎝ ⎠
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1
M
2
M
3
M
+ −
+ − + −
+ −
+ − + −
+ −
+ − + −
2 ( )
L
V s
+
( )
C
V s
( )
C
V s
+
L
V s
+
( )
C
V s
( )
C
V s
+
L
R
L
R
C1
M
2
M
3
M
Port 1 Port 2 Port 3
Port 4
Z Z
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( )
i m mn i n
b y t a =
1
( ) exp( )
mn
i i mn mn mn
L i
y t r p t
=
= −
TDR or FDTD
( ) ( )( ) ( )( ) ( ) ( )( ) ( )( ) ( ) ( )( )
11 22 12 21 21 1 11 22 12 21 11 22 12 21 21 2 11 22 12 21 21 3 11 22 12 21
(1 )(1 ) 2 1 (1 )(1 ) (1 )(1 ) 2 1 (1 )(1 ) 1 2 (1 )(1 ) M s Z M s Z M s Z ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ ξ − + + − + + − + − + − + + − = + + −
= =
( )
1 1 1 1* 1 1 1 1 1 1 1 1 1
( ) ( ) ( )
( )
i i i i i i k k kN i N i N i k k k i i i i i i k k k k k k k k r D r D r D
r r r M s s K s s j s j
s
α α β α β
= = = ≥ ≥ ≥
+ + + + −
= + + +
∑ ∑ ∑
R
L
R
1
M
2
M
3
M
Port 1 Port 2
Z Z
1 3 3 3 2 3
( ) ( ) ( ) eigen{Re } ( ) ( ) ( ) M j M j M j M j M j M j ω ω ω ω ω ω ⎡ ⎤ + − ≥ ⎢ ⎥ − + ⎣ ⎦
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L
R
L
R
4.3
r
ε =
Transmission line 50 Ohm
Port 2
S = 3 mil
GND
Port 1
Port 3
Port 4
Coupling Vias
L
R
L
R
1
M
2
M
3
M
Port 1 Port 2
Z Z
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0.1 1 10
GHz
0.01 0.02 0.03 0.04 0.05
Eigenvalue
asymmetric vias £f1 £f2
1 3 3 3 2 3
( ) ( ) ( ) eigen{Re } ( ) ( ) ( ) M j M j M j M j M j M j ω ω ω ω ω ω ⎡ ⎤ + − ≥ ⎢ ⎥ − + ⎣ ⎦
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( )
1 1 1 1
1 1 1 1 1 * 1 1 1 1
( ) ( ) ( )
( )
i i i i k k i i k
N i N i k k i i i i k k k k k r D r D N i k i i i k k k r D
r r M s s s s j r K s j
s
α α β α β
= = ≥ ≥ = ≥
+ + + + −
= + + +
M
2
3
M
+ −
+ − + −
+ −
+ − + −
+ −
+ − + −
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10 20 30 40 50 60 70 80
t (ps)
0.05 0.1 0.15 0.2 0.25
V 1 1 ( v
t )
3D-FDTD extracted model mode 54 extracted model mode 44
1 1 1 1
* 1 1 1 1 1 1 1 1 1
( ) ( ) ( )
i i i i i i k k k
N i N i N i k k k i i i i i i i k k k k k k k k r D r D r D
r r r M s s K s s j s j
α α β α β
= = = ≥ ≥ ≥
+ + + + −
R
LR
4.3
rε =
Transmission line 50 Ohm
Port 2 S = 3 mil
GND
Port 1 Port 3 Port 4
Coupling Vias
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10 20 30 40 50 60 70 80
t (ps)
0.05 0.1 0.15 0.2 0.25
V 2 2 ( v
t )
3D-FDTD extracted model mode 54 extracted model mode 44
0.005 0.015 0.025 0.035
V12 & V21 (volt)
1 1 1 1
* 1 1 1 1 1 1 1 1 1
( ) ( ) ( )
i i i i i i k k k
N i N i N i k k k i i i i i i i k k k k k k k k r D r D r D
r r r M s s K s s j s j
α α β α β
= = = ≥ ≥ ≥
+ + + + −
R
LR
4.3
rε =
Transmission line 50 Ohm
Port 2 S = 3 mil
GND
Port 1 Port 3 Port 4
Coupling Vias
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5 10 15 20 25 30
GHz
S 1 1 ( d B )
3D-FDTD S11 extracted model mode 54 extracted model mode 44 5 10 15 20 25 30
GHz
50 100 150 200
S 1 1 ( d e g )
3D-FDTD S11 extracted model mode 54 extracted model mode 44
5 10 15 20 25 30
GHz
S 2 1 ( d B )
3D-FDTD S21 extracted model mode 54 extracted model mode 44 5 10 15 20 25 30
GHz
50 100 150 200
S21 (deg)
3D-FDTD S21 extracted model mode 54 extracted model mode 44
LR
LR
4.3
rε =
Transmission line 50 Ohm
Port 2 S = 3 mil
GND
Port 1 Port 3 Port 4
Coupling Vias
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5 10 15 20 25 30
GHz
5
S 3 1 ( d B )
3D-FDTD S31 extracted model mode 54 extracted model mode 44 5 10 15 20 25 30
GHz
50 100 150 200
S 3 1 ( d e g )
3D-FDTD S31 extracted model mode 54 extracted model mode 44 5 10 15 20 25 30
GHz
S22 (dB)
3D-FDTD S22 extracted model mode 54 extracted model mode 44 5 10 15 20 25 30
GHz
50 100 150 200
S 2 2 ( d e g )
3D-FDTD S22 extracted model mode 54 extracted model mode 44
LR
LR
4.3
rε =
Transmission line 50 Ohm
Port 2 S = 3 mil
GND
Port 1 Port 3 Port 4
Coupling Vias
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Transmission line 50 Ohm
Port 2 S = 3 mil
GND
Port 1
L
R
L
R
4.3
r
ε =
Port 3
Port 4
GND
Differential Vias
L
R
L
R
1
M
3
M
Port 1 Port 2
Z Z
1
M
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1 3 3 3 2 3
( ) ( ) ( ) eigen{Re } ( ) ( ) ( ) M j M j M j M j M j M j ω ω ω ω ω ω ⎡ ⎤ + − ≥ ⎢ ⎥ − + ⎣ ⎦
1 10
GHz
0.02 0.025 0.03 0.035 0.04 0.045 0.05
E i g e n v a l u e
Differential via £f1 £f2
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10 20 30 40 50 60 70 80
t (ps)
0.05 0.1 0.15 0.2 0.25
V11 (volt)
3D-FDTD extracted model
0.01 0.02 0.03 0.04
V 1 2 & V 2 1 ( v
t )
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5 10 15 20 25 30
GHz
10
S11 (dB)
3D-FDTD S11 extracted model S11 5 10 15 20 25 30
GHz
50 100 150 200
S11 (deg)
3D-FDTD S11 extracted model 5 10 15 20 25 30
GHz
S21 (dB)
3D-FDTD S21 extracted model S21 5 10 15 20 25 30
GHz
50 100 150 200
S21 (deg)
3D-FDTD S21 extracted model
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5 10 15 20 25 30
GHz
5
S31 (dB)
3D-FDTD S31 extracted model S31 5 10 15 20 25 30
GHz
50 100 150 200
S31 (deg)
3D-FDTD S31 extracted model 5 10 15 20 25 30
GHz
S41 (dB)
3D-FDTD S41 extracted model S41 5 10 15 20 25 30
GHz
50 100 150 200
S41 (deg)
3D-FDTD S41 extracted model
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Introduction Signal Integrity Simulation in SPICE
A case Study: Driver Board of TFT Display Panel
TDR Concept and Layer Peeling Technique (one port) Macro-model Synthesis for Coupled Discontinuities
Challenge of SI Modeling for Real PCB and Package Summary
NTU
Challenge of Modeling the Real PCB and Package
4-layer Motherboard for Desktop Computer (PCB)
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Challenges for Modeling the Real PCB and Package
Top side Bottom side
4-layer Motherboard for Desktop Computer (PCB)
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Challenges for Modeling the Real PCB and Package
4-layer BGA Package, 37.5mm × 37.5mm, 788 pin balls
Ground Layer (layer 2) Power Layer (layer 3)
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Challenges for Modeling the Real PCB and Package
Real PCB and Packages
In SI simulation, we need to think
How accurate you need? How complicated your circuits are? How much (computing) resources you have?
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Challenges for Modeling the Real PCB and Package
Material Characteristics:
' ''
f f j f ε ε ε = −
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Challenges for Modeling the Real PCB and Package in High-speed Circuits
Signal Propagation Characteristics:
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Challenges for Modeling the Real PCB and Package in High-speed Circuits
Power distribution networks characteristics
Challenges: (how accurate?)
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Challenges for Modeling the Real PCB and Package in High-speed Circuits
Power Network Pre-drive Circuits
IVDD Ipd Ishot Isig
VDD sig shot pd clamp
IBIS Model for Power Noise modeling
Isig are considered in IBIS model (pull up and pull down current) The pre-drive current Ipd and shot-through current Ishot are not considered in IBIS model
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Challenges for Modeling the Real PCB and Package in High- speed Circuits
IBIS Model for SSN modeling
Pull up current Pre-drive current
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As an example, a driver PCB for TFT display panel is modeled by two
models. TDR concept and layer peeing technique for extracting equivalent circuit models is introduced based on time domain response. A synthesis approach for macro equivalent circuit model for coupled discontinuity is also discussed. Challenges for SI design tool in modeling the real PCB and package in high- speed circuits are discussed. They includes material characteristics, signal propagation characteristics, power distribution networks, and IBIS model for SSN.