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SEQUENTIAL Part 1 Samira Khan The slides are prepared by Charles Reiss 1 registers PC updates every clock cycle register output register input 2 state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC

  1. SEQUENTIAL Part 1 Samira Khan The slides are prepared by Charles Reiss 1

  2. registers PC updates every clock cycle register output register input 2

  3. state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC R[srcB] Instr. Mem. register file srcA srcB R[srcA] dstE Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF 3

  4. state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC R[srcB] Instr. Mem. register file srcA srcB R[srcA] dstE Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF 3

  5. state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC R[srcB] Instr. Mem. register file srcA srcB R[srcA] dstE Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF 3

  6. state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC R[srcB] Instr. Mem. register file srcA srcB R[srcA] dstE Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF 3

  7. state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC R[srcB] Instr. Mem. register file srcA srcB R[srcA] dstE Stat next R[dstE] dstM next R[dstM] Data Mem. ZF/SF 3

  8. memories write enable? value in memory input to write address input time data output address input read enable? to write Instr. input address data output Mem. Data address data Mem. 4

  9. memories write enable? value in memory input to write address input time data output address input read enable? to write Instr. input address data output Mem. Data address data Mem. 4

  10. memories write enable? value in memory input to write address input time data output address input read enable? to write Instr. input address data output Mem. Data address data Mem. 4

  11. register file register file %rax, %rdx, … reg values read reg #s write reg #s data to write register number input register value output time register number input data input value in register write register #15: write is ignored read register #15: value is always 0 5

  12. register file register file %rax, %rdx, … reg values read reg #s write reg #s data to write register number input register value output time register number input data input value in register write register #15: write is ignored read register #15: value is always 0 5

  13. register file register file %rax, %rdx, … reg values read reg #s write reg #s data to write register number input register value output time register number input data input value in register write register #15: write is ignored read register #15: value is always 0 5

  14. register file register file %rax, %rdx, … reg values read reg #s write reg #s data to write register number input register value output time register number input data input value in register write register #15: write is ignored read register #15: value is always 0 5

  15. ALUs ALU A OP B A B operation select Operations needed: add — addq , addresses sub — subq xor — xorq and — andq more? 6

  16. simple ISA 1: addq addq %rXX, %rYY encoding: %rXX %rYY (two 4-bit register #s) 1 byte instructions, no opcode no other instructions 7

  17. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  18. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  19. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  20. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  21. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  22. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  23. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  24. addq CPU initially: rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx PC = 0x00, rdx = 3 rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6 after cycle 1: PC = ????, rbx = 2, PC next R[dstM] Instr. Mem. register file srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM Data rax = 1, Mem. ZF/SF %rXX %rYY split add (contains ALU) /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, 8

  25. Simple ISA 2: jmp jmp label encoding: 8-byte little-endian address 8 byte instructions, no opcode 9

  26. jmp CPU Data after cycle 3: PC = 0x00 after cycle 2: PC = 0x08 after cycle 1: PC = 0x10 PC = 0x00 initially: /* 0x10: */ jmp 0x08 /* 0x08: */ jmp 0x00 /* 0x00: */ jmp 0x10 ZF/SF Mem. next R[dstM] PC dstM next R[dstE] dstE R[srcB] R[srcA] srcB srcA register file Mem. Instr. 10

  27. jmp CPU Data after cycle 3: PC = 0x00 after cycle 2: PC = 0x08 after cycle 1: PC = 0x10 PC = 0x00 initially: /* 0x10: */ jmp 0x08 /* 0x08: */ jmp 0x00 /* 0x00: */ jmp 0x10 ZF/SF Mem. next R[dstM] PC dstM next R[dstE] dstE R[srcB] R[srcA] srcB srcA register file Mem. Instr. 10

  28. jmp CPU Data after cycle 3: PC = 0x00 after cycle 2: PC = 0x08 after cycle 1: PC = 0x10 PC = 0x00 initially: /* 0x10: */ jmp 0x08 /* 0x08: */ jmp 0x00 /* 0x00: */ jmp 0x10 ZF/SF Mem. next R[dstM] PC dstM next R[dstE] dstE R[srcB] R[srcA] srcB srcA register file Mem. Instr. 10

  29. = 0 or 1 or 2 or 3 multiplexers 0 d 1 1 c 0 1 b 1 0 a output (many bits) 0 MUX select bit 0 select bit 1 truth table: = a or b or c or d select output d c b a 11

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