SLIDE 1
SEQUENTIAL Part 1
Samira Khan The slides are prepared by Charles Reiss
1
registers
PC
updates every clock cycle
register output register input
2
SEQUENTIAL Part 1 Samira Khan The slides are prepared by Charles - - PowerPoint PPT Presentation
SEQUENTIAL Part 1 Samira Khan The slides are prepared by Charles - - PowerPoint PPT Presentation
SEQUENTIAL Part 1 Samira Khan The slides are prepared by Charles Reiss 1 registers PC updates every clock cycle register output register input 2 state in Y86-64 logic to PC c i g o l to reg c i g o l ALU) (with logic PC
SLIDE 2
SLIDE 3
state in Y86-64
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF Stat
logic logic (with ALU) l
- g
i c
to reg
l
- g
i c
to PC
3
SLIDE 4
state in Y86-64
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF Stat
logic logic (with ALU) l
- g
i c
to reg
l
- g
i c
to PC
3
SLIDE 5
state in Y86-64
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF Stat
logic logic (with ALU) l
- g
i c
to reg
l
- g
i c
to PC
3
SLIDE 6
state in Y86-64
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF Stat
logic logic (with ALU) l
- g
i c
to reg
l
- g
i c
to PC
3
SLIDE 7
state in Y86-64
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF Stat
logic logic (with ALU) l
- g
i c
to reg
l
- g
i c
to PC
3
SLIDE 8
memories
Instr. Mem. data address Data Mem. data output address input to write write enable? read enable? address input data output
time
address input input to write value in memory
4
SLIDE 9
memories
Instr. Mem. data address Data Mem. data output address input to write write enable? read enable? address input data output
time
address input input to write value in memory
4
SLIDE 10
memories
Instr. Mem. data address Data Mem. data output address input to write write enable? read enable? address input data output
time
address input input to write value in memory
4
SLIDE 11
register file
register file
%rax, %rdx, … reg values read reg #s write reg #s data to write
register number input register value output
time
register number input data input value in register
write register #15: write is ignored read register #15: value is always 0
5
SLIDE 12
register file
register file
%rax, %rdx, … reg values read reg #s write reg #s data to write
register number input register value output
time
register number input data input value in register
write register #15: write is ignored read register #15: value is always 0
5
SLIDE 13
register file
register file
%rax, %rdx, … reg values read reg #s write reg #s data to write
register number input register value output
time
register number input data input value in register
write register #15: write is ignored read register #15: value is always 0
5
SLIDE 14
register file
register file
%rax, %rdx, … reg values read reg #s write reg #s data to write
register number input register value output
time
register number input data input value in register
write register #15: write is ignored read register #15: value is always 0
5
SLIDE 15
ALUs
ALU A OP B A B
- peration select
Operations needed: add — addq, addresses sub — subq xor — xorq and — andq more?
6
SLIDE 16
simple ISA 1: addq
addq %rXX, %rYY encoding:
%rXX %rYY (two 4-bit register #s)
1 byte instructions, no opcode
no other instructions
7
SLIDE 17
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 18
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 19
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 20
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 21
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 22
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 23
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 24
addq CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
%rXX %rYY
split add (contains ALU)
/* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = ????, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = ????, rax = ??, rbx = ??, rdx = ?? plus one /* 0x00: */ addq %rax, %rdx /* 0x01: */ addq %rbx, %rdx initially: PC = 0x00, rax = 1, rbx = 2, rdx = 3 after cycle 1: PC = 0x01, rax = 1, rbx = 2, rdx = 4 after cycle 2: PC = 0x02, rax = 1, rbx = 2, rdx = 6
8
SLIDE 25
Simple ISA 2: jmp
jmp label encoding: 8-byte little-endian address
8 byte instructions, no opcode
9
SLIDE 26
jmp CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF /* 0x00: */ jmp 0x10 /* 0x08: */ jmp 0x00 /* 0x10: */ jmp 0x08 initially: PC = 0x00 after cycle 1: PC = 0x10 after cycle 2: PC = 0x08 after cycle 3: PC = 0x00
10
SLIDE 27
jmp CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF /* 0x00: */ jmp 0x10 /* 0x08: */ jmp 0x00 /* 0x10: */ jmp 0x08 initially: PC = 0x00 after cycle 1: PC = 0x10 after cycle 2: PC = 0x08 after cycle 3: PC = 0x00
10
SLIDE 28
jmp CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF /* 0x00: */ jmp 0x10 /* 0x08: */ jmp 0x00 /* 0x10: */ jmp 0x08 initially: PC = 0x00 after cycle 1: PC = 0x10 after cycle 2: PC = 0x08 after cycle 3: PC = 0x00
10
SLIDE 29
multiplexers
MUX a b c d
- utput
select = 0 or 1 or 2 or 3 = a or b or c or d truth table: select bit 1 select bit 0
- utput (many bits)
a 1 b 1 c 1 1 d
11
SLIDE 30
multiplexers
MUX a b c d
- utput
select = 0 or 1 or 2 or 3 = a or b or c or d truth table: select bit 1 select bit 0
- utput (many bits)
a 1 b 1 c 1 1 d
11
SLIDE 31
multiplexers
MUX a b c d
- utput
select = 0 or 1 or 2 or 3 = a or b or c or d truth table: select bit 1 select bit 0
- utput (many bits)
a 1 b 1 c 1 1 d
11
SLIDE 32
Simple ISA 3: Jmp or No-Op
actual subset of Y86-64 jmp LABEL — encoded as 0x70 + address nop — encoded as 0x10
12
SLIDE 33
jmp+nop CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
split
MUX
1 if jmp 0 if nop
- pcode
dest
+ 1 (nop size)
nop 1 jmp Dest 7 Dest
nop jmp dest 1 icode valC valP PC not in listing
13
SLIDE 34
jmp+nop CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
split
MUX
1 if jmp 0 if nop
- pcode
dest
+ 1 (nop size)
nop 1 jmp Dest 7 Dest
nop jmp dest 1 icode valC valP PC not in listing
13
SLIDE 35
jmp+nop CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
split
MUX
1 if jmp 0 if nop
- pcode
dest
+ 1 (nop size)
nop 1 jmp Dest 7 Dest
nop jmp dest 1 icode valC valP PC not in listing
13
SLIDE 36
jmp+nop CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
split
MUX
1 if jmp 0 if nop
- pcode
dest
+ 1 (nop size)
nop 1 jmp Dest 7 Dest
nop jmp dest 1 icode valC valP PC not in listing
13
SLIDE 37
jmp+nop CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
split
MUX
1 if jmp 0 if nop
- pcode
dest
+ 1 (nop size)
nop 1 jmp Dest 7 Dest
nop jmp dest 1 icode valC valP PC not in listing
13
SLIDE 38
exercise: nop/add CPU
Let’s say we wanted to make nop+add CPU. Where would need MUXes?
- A. before one or both of the register file ‘register number to read’
inputs
- B. before the PC register’s input
- C. before one of the register file ‘register number to write’ inputs
- D. before one of the register file ‘register value to write’ inputs
- E. before the instruction memory’s address input
14
SLIDE 39
Summary
each instruction takes one cycle divided into stages for design convenience read values from previous cycle send new values to state components control what is sent with MUXes
15
SLIDE 40
simple ISA 4: mov-to-register
irmovq $constant, %rYY rrmovq %rXX, %rYY mrmovq 10(%rXX), %rYY
16
SLIDE 41
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 42
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 43
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 44
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 45
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 46
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 47
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17
SLIDE 48
mov-to-register CPU
PC
Instr. Mem.
register file
srcA srcB R[srcA] R[srcB] dstE next R[dstE] dstM next R[dstM]
Data Mem.
ZF/SF
Data in Addr in Data out
split
MUX
convert
- pcode
immediate + (ALU) +2 +10
rrmovq rA, rB 2 0 rA rB irmovq V, rB 3 F rB mrmovq D(rB), rA 5 0 rA rB V D
17