Sample and Hold Dag T. Wisland Spring 2014 Outline Sample and hold - - PowerPoint PPT Presentation

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Sample and Hold Dag T. Wisland Spring 2014 Outline Sample and hold - - PowerPoint PPT Presentation

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INF4420 Sample and Hold Dag T. Wisland Spring 2014 Outline Sample and hold basics Non ideal behavior Sample and hold circuits Spring 2014 Sample and hold 2 Introduction Take a snapshot of the input signal at an instant

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INF4420

Sample and Hold

Dag T. Wisland Spring 2014

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SLIDE 2

Spring 2014 Sample and hold 2

Outline

  • Sample and hold basics
  • Non‐ideal behavior
  • Sample and hold circuits
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Introduction

  • Take a “snapshot” of the input signal at an

instant (sampling)

  • Need “memory” to keep the signal value
  • We know how to store digital values (latches and

flip‐flops)

  • Capacitor as a memory element

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Introduction

  • Signal, x(t), sampled at discrete time points, nT.

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Introduction

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Basic circuit

  • Sample and hold vs. track and hold

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Sample and hold

Typically used to hold the input constant while converting from analog to digital. Limits performance, imperfections add directly to the input signal. In a later lecture we will see how sampling affects the signal.

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Non‐ideal behaviour

  • Hold step (signal dependence)
  • Coupling from output to sampled signal
  • Finite speed
  • Droop
  • Aperture jitter
  • Noise …

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Finite speed

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Finite speed

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Settling time

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Charge injection

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  • Switch transistor has channel

charge when “on”

  • Charge flows out of the

channel when the transistor turns off

  • Assume half the charge to

source and half to drain. (Depends …)

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Charge injection

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Clock feedthrough

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Jitter

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Closed loop S/H

Generic solution to mitigate non‐ideal properties Gain + Negative feedback

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A better (?) S/H

  • Switch configures circuit in two states. Analyze

separately

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A better (?) S/H

  • Eliminates non‐linearity of output buffer +
  • High input impedance +
  • Open loop opamp when switch is open –
  • Stability –
  • Can add switches to make sure the opamp is

closed loop when holding

Spring 2014 Sample and hold 18

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A better S/H

Spring 2014 Sample and hold 19

  • No signal dependent charge injection +
  • No signal dependent clock jitter +
  • Stability (worse than before) –
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Inverting T/H

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Lowpass in track mode and signal independent charge

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Non‐inverting with cancelation

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Miller hold capacitance

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Switched capacitor (SC) S/H

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Recycling S/H

Adds buffering

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SC S/H with lowpass filtering

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Bottom plate sampling

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High speed bipolar T/H

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Fully differential sample and hold

  • “Real” S/Hs are fully differential
  • We can modify many of the S/H discussed today

to become fully differential

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