Reliability and Lifetime of Electronics in the cold : past, present - - PowerPoint PPT Presentation

Reliability and Lifetime

• f Electronics in the cold :

past, present and future

Veljko Radeka radeka@bnl.gov DUNE CE Workshop 07/16‐18/2018

Outline

• 1. CE before cold CMOS: JFETs, discrete and hybrid circuits, from

the first JFET (1963) until NA48‐62 and ATLAS: “Will thermal contraction/expansion cause damage?”

• 2. MicroBooNE: CMOS FE ASIC, 3 years of stable operation in

Lar: “Has anything changed?”

• 3. “Reliability” vs “Lifetime”: Random Failures vs Aging
• 4. CMOS hot electron effects (HCE): How to avoid them?
• 5. Accelerated stress testing of CMOS and HV capacitors:
• 6. Ingredients of “reliability”
• V. Radeka

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Cryogenic front-end based on JFETs – Helios-NA34 Liquid Argon calorimeter (1985-9) ‐‐ Ceramic hybrid with co‐ fired traces and surface mount components ‐‐ 576 preamplifiers – Operation: 4 years, multiple cool‐downs – Failure: 1, =<0.2% caused by a mechanical contact

It all started with: Single cold JFET with Ge detectors (1965‐8)

• V. Radeka

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Liquid Krypton calorimeter in NA48-NA62

– JFET preamplifiers in LKr: 13,212 channels; surface mounted components – Operated at 5 kV; HV caps had to be realized in PCBs – Failures

• ~50 because of an HV accident in

1998

• ~25 cold electronics failures after

1998,

< 0.2%

– Always kept at LKr temperature since 1998 – Operation:

• 20 years so far
• Expected to be in operation for

>20 years 15 tons

• f LKr

Reliability of Cold Electronics wrt thermal contraction‐expansion PCB and Cold Electronics in ATLAS:

• ATLAS LAr Calorimeter

– 182,468 readout channels

• EM Barrel Mother Board and Summing Board

– EMB has ~110,000 detector channels read out by 896x128-ch FEBs – 960 Mother Boards (MB) – 7,168 Summing Boards (SB) – 20,480 resistor network chips, 0.1% – ~110,000 protection diodes on MBs/SBs

• EM Barrel Calorimeter has been cold since

2004 – Operation: 14 years so far – MB/SB will remain in operation without upgrade for super LHC

• ‘Inoperative’ channels <0.5%, as of

05/10/2011

• ‘Dead’ channels in the cryostat

~0.02% since 2008 EMB Mid/Back MB+SB Assembly EMB Wheel C

• Preamplifier ASIC based on GaAs

– HEC has ~5,600 detector channels read out by 48x128‐ch FEBs – 320 PSBs installed on HEC wheels, 5 different types – Total ~35,000 cold preamplifier channels, each preamplifier ASIC has 8 channels

• HEC Calorimeter has been cooled

down since 2005

– Operation: 14 years so far – HEC cold electronics will remain in operation; no upgrade required

• Dead channels ~0.37%

HEC Type C PSB HEC Rear Wheel

PCB and Cold Electronics in ATLAS HEC

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PC board and hybrid circuits (Si JFETs and GaAs ICs)

• After a few initial failures at installation and

commissioning, no failures (so far for 10 to 20 years).

• In the examples given, fewer dead channels

within the cryostats than in the warm electronics

• utside.
• “So, the pc board technology in LAr works, but

we are concerned about CMOS ….”

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MicroBooNE long term stability of average MIP response,

• incl. argon purity variations

MicroBooNE publication

<0.2 % gain variation

MicroBooNE Gain Stability

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Analysis by: Brian Kirby

MB FE ASIC Transistor Level Design

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• Some hot electrons exceed the energy required to create an electron‐

hole pair, , resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current is expressed as

• A very small fraction of hot electrons exceeds the energy required to

create an interface state at the Si‐SiO2 interface, , for electrons (~4.6eV for holes).

• Physical model of the generation of interface states can be described as

hot electrons that have enough energy to surmount Si ‐ SiO2 barrier (3.1eV) and break the silicon‐hydrogen bond (0.3eV ) generating a trivalent silicon atom (interface state) and a hydrogen atom like

1.3

i

eV  

1

i m

q E sub ds

I C I e

  



q = electron charge λ=electron mean free path Em= electric field Ids= drain‐source current W= channel width C1, C2 ‐ constants

dsat ds m

V V E   3.7

it

eV  

If the silicon recombines with the hydrogen, no interface state will appear. If the hydrogen atom diffuses away from the interface, interface state will be generated. The total barrier for hot electrons to inject can be calculated as φit = 3.1eV + 0.3eV = 3.4eV, close to the experimental result (~ 3.7eV ‐ 4.1eV).

Hot Carrier Effect (HCE)

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IVCC drops 1% as degradation criteria

COTS: No access to transistor design, but a known process, TSMC 350nm ADC 7274 Lifeme Projecon → Vds=2.5 V well below Vnode=3.6 V

3.6V, 150 years

Reduced VDS results in making HCE negligible and a very long extrapolated life time. (005) 5.25V, 800 hours is estimated

Hot electrons: Why is the dependence of Lifetime

• n Vds so strong?

Hot electrons: Why is the dependence of Lifetime

• n Vds so strong?

The lifetime is given by, Electrons in the MOS channel reach energies well above thermal both at 300K and at 77K . However the mean electron energy, , at the electric field in the range Em ≥100kV/cm. At 77K it is slightly higher, Only a tiny fraction of “hot” electrons reaches the much higher energy required to create an interface state. This makes the exponent in the relation for the lifetime very large, Since , the ratio of lifetimes for two slightly different values of Vds is given by,

100

he m

q E meV    

77 300

1.06

he K he K

  

3.7

it

eV   40 4

it it he m

q E       

   

2

1 1

it he it he

ds ds

C e e I W I W

   

  

2 1 2 1

ln 1

it ds he ds

V V             

2 1 1 2

1.06 10

ds ds

V for V     

m ds

E V 

Failure Rate/MTBF(MTTF) and Wear(Aging)

• MTBF (Mean Time Between Failures) and Failure Rate λ=1/MTBF

approach to Reliability, assumes a random process, where the failure rate is constant and the distribution of time intervals between failures is given by Poisson statistics. It can be controlled by the design, choice of components, and various quality control tools.

• Reliability is defined as the probability that a component (transistor,

circuit, subsystem, or entire system) will operate, as specified, over a given time without failure. In terms of Failure Rate, or MTBF, it is given by,

• Mission/Service Life is useful life as limited by any mechanism, random

failure, or wear/aging, uniform and understood for a given class of components.

• Wear/aging is given by the physical/chemical processes, with all devices
• f the same type subject to the same process. It can be controlled only by

the design and the operating conditions.

0.999..

t t MTBF

R e e MTBF

  

     

Sense Wire Bias Circuit: “What about me?!”

• FE ASIC input impedance ~50

(only input stage is shown).

• L is a component of the ESD

protection circuit.

• 22nF taken into account in

accurate Cc calculations

• CC minimum value given by charge calibration accuracy and capacitor tolerance:
• with CW~200 pF, and a 10% precision in ∆CC/CC , to reach for ∆Qi/Qi=0.5% requires

CC>4 nF.

• E.g., Choose 4.7 nF @ ~10% tolerance , or 2.2 nF @ 5% tolerance
• CC voltage rating: WVDC>2 x operating voltage
• CW/CC ratio determines the fraction of charge Qi is NOT being transferred to the

amplifier therefore impacts signal to noise ratio. For example, if CC=2.2nF, ~8% of signal charge is not measured by the amplifier. ∆

• ≅
• ∆

Besides CMOS, capacitors deserve attention:

• The highest risk for the sense wire capacitor Cc is it’s

cost (~$1.30), comparable to the FE ASIC cost/channel.

• The type of capacitor used so far, well proven, e.g.,

LAr HEC in ATLAS: Kemet C2225X392JGGACTU, CAP CER 3900PF 2KV C0G/NP0 2225, +/‐5% tolerance.

• Finding a lower cost capacitor is a risky enterprise, it

may result in a really “cheap” capacitor ….

• Capacitor life time and accelerated stress testing is a

separate field. It requires digging into chemical kinetics, Eyring equation and similar ….

• V. Radeka

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Ingredients of “reliability” in LAr

• Start with:
• ASIC design below the HCE domain (Vds<Vnode)
• PC board assemblies designed and fabricated

to survive repeated immersions in LN2.

• Capacitors operating voltage Vop<WVDC/2
• Connectors and cables, a testing challenge …
• …..
• Formal QA process for everything …
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Backup Slides

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Choice of the Bias Circuit Components

• R1C1 is a filter for the bias bus on the CR board (40 to 48 wires). It should be very

effective in removing ripples in the bias power supply.

• Chosen value: R1=2.2M, C1=50nF, tolerance not critical
• Rb minimum value >20M for negligible noise contribution to the preamps. It limits

the current flowing through the bias network in case of a shorted sense wire.

• Chosen value: 50M, tolerance not critical
• R1/Rb ratio determines the fractional drop in voltage on the entire wire group if one
• r more wires are shorted to another wire plane. To minimize impact to the electron

transparency in the region covered by this wire group, choose R1<<Rb.

• Signal charge Qi transfer onto the feedback capacitance CF is fast (time constant

CwRin~ 10 ns to minimize wire‐to‐wire crosstalk. RbCc time constant >~25 x electron drift time, to make any undershoot due to ac coupling small and easily correctable: RbCc=50Mx4.7nF~=230 ms

HV Capacitors in LAr Detectors

Detector LAr calo Capacita nce [nF] C77/C300 Dielectric WVDC Vop Number of units Failures/ time ISR/ Impacto meter 100 ~1 Reconstit . mica 3.5 kV 2 kV ~100 0/6 years HELIOS EM, H calo 50 ~1/3 Ceramic 5 kV 2 kV ~574 0/5 years ATLAS FW calo 12 nF ~1 Ceramic NPO 500 V 1 kV 250 V 500 V 7671 10^9Hz/cm^2 0/10 years 0.5Grad MicroBo

• NE

5 ~1 Ceramic NPO 1 kV 440 V ~5000 0/3 years

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