Ral Torrego Ikerlan-IK4 rtorrego@ikerlan.es INDEX Introduction - - PowerPoint PPT Presentation

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Ral Torrego Ikerlan-IK4 rtorrego@ikerlan.es INDEX Introduction - - PowerPoint PPT Presentation

Oct 13, 2022 567 likes •739 views

OQPSK COGNITIVE MODULATOR FULLY FPGA-IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS Ral Torrego Ikerlan-IK4 rtorrego@ikerlan.es INDEX Introduction Software Defined Radios / Cognitive Radios Rapid

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OQPSK COGNITIVE MODULATOR FULLY FPGA-IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

Raúl Torrego Ikerlan-IK4 rtorrego@ikerlan.es

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

2 Index

INDEX

  • Introduction
  • Software Defined Radios / Cognitive Radios
  • Rapid prototyping tools and FPGA Partial Reconfiguration
  • System Implementation
  • OQPSK modulator
  • Power Spectral Density estimator
  • Partial Reconfiguration and system architecture
  • Partial reconfiguration and rapid prototyping tools
  • Work algorithm
  • Test framework
  • Measurements
  • Conclusions and future work
  • Questions
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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

3

INTRODUCTION

  • Requirements to be met by communication systems:
  • High data rate, heterogeneous communication

standard compatibility, reliable communications, high battery life, small size, low price...

  • Technological answer:
  • Software Defined Radios (Ability to change)
  • Cognitive Radios (Ability to sense)
  • Intelligent Radios (Ability to learn)

Introduction (1 of 3)

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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INTRODUCTION

  • SDR design environment:
  • Communication

system where a single piece of hardware has different functionalities in different times

Rapid prototyping tools FPGA partial reconfiguration (PR) · Graphical programming, no code writing. · Early functional simulations ·Easy debugging · Design flexibility · Hardware reuse. · Power save Fit perfectly

Introduction (2 of 3)

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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INTRODUCTION

  • Proposed application
  • Cognitive Radios in wireless industrial

communications

  • Proposed implementation
  • OQPSK modulator (WirelessHART/IEEE802.11.4)
  • Channel sensing
  • Transmission in free channel

Introduction (3 of 3)

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

6 Implementation (1 of 7)

IMPLEMENTATION

  • Two signal processing tasks
  • OQPSK modulator
  • Power Spectral Density estimator
  • Chosen rapid prototyping tool
  • Xilinx’s System Generator
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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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IMPLEMENTATION

  • OQPSK modulator implementation

Implementation (2 of 7)

  • Basic characteristics:
  • 2 Mbps
  • FI: 5-10 MHz (PR implemented)
  • Output filter: 64 tap, 0.25 roll-off

Data acquisition Differential encoder Oscillator Modulator

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

8

IMPLEMENTATION

  • PSD estimator implementation

Implementation (3 of 7)

  • Basic characteristics:
  • FFT: 64 tap
  • Fs: 61.44 MHz
  • Resolution: 1 MHz

FFT Power detector

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IMPLEMENTATION

  • PR architecture

Implementation (4 of 7)

  • Basic characteristics:
  • PR controlled by

uBlaze

  • VHDL coded memory

and ADC/DAC controllers.

  • ICAP internal access

port

  • 2 PR implementations
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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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IMPLEMENTATION

  • FPGA partial reconfiguration and rapid prototyping tools
  • Not a standardized procedure
  • Possible but potentially dangerous
  • Necessary steps

 Extraction of the non-reconfigurable FPGA resources (DCM, BUFG...)  Static and reconfigurable port concordance  Manage properly data exchanges

Implementation (5 of 7)

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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IMPLEMENTATION

  • Working Algorithm

Implementation (6 of 7) FPGA power up FPGA configuration from platform FLASH Initialization Read PSD estimator data

  • Partial bitstream copy from

FLASH to RAM/BRAM

  • ICAP initialization

Analysis & decision Partial reconfiguration New frequency

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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IMPLEMENTATION

  • Test framework

Implementation (7 of 7)

MODULATOR

CHANNEL

DISTURBANCE VECTOR SIGNAL ANALYZER

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

13 Measurements (1 of 2)

  • Resource measurements
  • Small form factor (<35%)
  • PSD estimator, main resource consumer (data

processing) – 10%

  • uBlaze system, main resource consumer (overall)

– 19% MEASUREMENTS

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

14 Measurements (2 of 2)

  • Reconfiguration time measurements
  • ICAP theoretical speed: 400 MBps
  • Measured speed: 4.5 – 8 MBps
  • Suboptimal ICAP implementation
  • Theoretical reconfiguration times below the

millisecond MEASUREMENTS

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

15 Conclusions and future work

  • Conclusions
  • Simple application but valid as a proof-of-concept
  • Benefits: resource and power reduction, reliable

communications and easy design

  • Main drawback: reconfiguration time and hand

made operations

  • Future work
  • Develop an optimized own ICAP
  • Develop a design methodology- reconfigurable

function analysis

  • Framework appliance to a multi-standard

modulator CONCLUSIONS AND FUTURE WORK

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OQPSK COGNITIVE MODULATOR FULLY FPGA- IMPLEMENTED VIA DYNAMIC PARTIAL RECONFIGURATION AND RAPID PROTOTYPING TOOLS

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QUESTIONS