PROGRAMMING ANALOG DEVICES WITH JAUNT AND ARCO 2 Programmable - - PowerPoint PPT Presentation

PROGRAMMING ANALOG DEVICES WITH JAUNT AND ARCO

SARA ACHOUR / MIT CSAIL MARTIN RINARD / MIT CSAIL

INTRODUCTION 2

· ES = kf ⋅ E ⋅ S − kr ⋅ ES x′′+ ax′+ x + ax2 = c3 L ⋅ I′′+ R ⋅ I′+ C−1 ⋅ I = 0 x′′+ c1x′+ c2x′′ = 0

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

Dynamical Systems Programmable 
 Analog Devices

INTRODUCTION

DYNAMICAL SYSTEMS MODEL THE PHYSICAL WORLD

3

· ES = kf ⋅ E ⋅ S − kr ⋅ ES x′′+ ax′+ x + ax2 = c3 L ⋅ I′′+ R ⋅ I′+ C−1 ⋅ I = 0 x′′+ c1x′+ c2x′′ = 0

INTRODUCTION 4

· ES = kf ⋅ E ⋅ S − kr ⋅ ES x′′+ ax′+ x + ax2 = c3 L ⋅ I′′+ R ⋅ I′+ C−1 ⋅ I = 0 x′′+ c1x′+ c2x′′ = 0

DYNAMICAL SYSTEMS MODEL BIOLOGICAL PROCESSES

INTRODUCTION

BIOLOGICAL DYNAMICAL SYSTEMS

5

· ES = kf ⋅ E ⋅ S − kr ⋅ ES E = E0 − ES S = S0 − ES

S E S E

state variables model physical quantities

INTRODUCTION

BIOLOGICAL DYNAMICAL SYSTEMS

6

· ES = kf ⋅ E ⋅ S − kr ⋅ ES E = E0 − ES S = S0 − ES

differential equations specify continuous dynamics

• f state variables over time

INTRODUCTION

GOAL: SIMULATING BIOLOGICAL DYNAMICAL SYSTEMS

7

· ES = kf ⋅ E ⋅ S − kr ⋅ ES E = E0 − ES S = S0 − ES

given initial state of system: compute values of state variables over time

E0 = 6800 S0 = 4400 ES(0) = 0

INTRODUCTION

GOAL: SIMULATING BIOLOGICAL DYNAMICAL SYSTEMS

8

· ES = kf ⋅ E ⋅ S − kr ⋅ ES E = E0 − ES S = S0 − ES

plot molecule counts/concentrations of compounds

• ver time

E0 = 6800 S0 = 4400 ES(0) = 0

2 4 6 8 10 time (su) 2000 4000 6000 molecules

INTRODUCTION 9

• direct mapping
• variables → current, voltage
• dynamics → circuit physics
• straightforward simulation
• power up circuit
• measure current, voltage over time
• 1970-2010: Age of Digital Computing
• Analog computes out of fashion

ANALOG COMPUTING CIRCA 1950

INTRODUCTION 10

• same computational model
• modernized hardware
• modern semiconductor

technologies

• new capabilities
• powerful, heavily optimized

building blocks

• digital reprogrammability
• exploit analog noise

PROGRAMMABLE ANALOG DEVICES

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

INTRODUCTION 11

• physical behavior
• voltage/current operating ranges
• circuit noise [thermal/shot/flicker]
• complex building blocks
• non-linear, non-convex
• space limitations
• limitations on number of

available blocks and connections

• requires creativity when

configuring device

PROGRAMMING CHALLENGES FOR ANALOG DEVICES

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

INTRODUCTION 12

· ES = kf ⋅ E ⋅ S − kr ⋅ ES x′′+ ax′+ x + ax2 = c3 L ⋅ I′′+ R ⋅ I′+ C−1 ⋅ I = 0 x′′+ c1x′+ c2x′′ = 0

Dynamical Systems

A COMPILER FOR PROGRAMMABLE ANALOG DEVICES

Programmable 
 Analog Devices

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

INTRODUCTION 13

· ES = kf ⋅ E ⋅ S − kr ⋅ ES x′′+ ax′+ x + ax2 = c3 L ⋅ I′′+ R ⋅ I′+ C−1 ⋅ I = 0 x′′+ c1x′+ c2x′′ = 0

Dynamical Systems compose complex algebraic building blocks reason about operating ranges + circuit noise automatically automatically Programmable 
 Analog Devices

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

INTRODUCTION 14

· ES = kf ⋅ E ⋅ S − kr ⋅ ES x′′+ ax′+ x + ax2 = c3 L ⋅ I′′+ R ⋅ I′+ C−1 ⋅ I = 0 x′′+ c1x′+ c2x′′ = 0

Dynamical Systems compose complex algebraic building blocks reason about operating ranges + circuit noise automatically automatically FUNDAMENTALLY NEW COMPILATION TECHNIQUES Programmable 
 Analog Devices

OUTLINE 15

• Background: overview of compilation problem
• Arco Compiler1: automatically configure analog devices to simulate

dynamical systems.

• Jaunt Solver2: automatically scales dynamical systems to execute

analog hardware with operating range constraints.

• Closing Remarks

TALK OUTLINE

1. Configuration Synthesis for Programmable Analog Devices with Arco. Sara Achour, Rahul Sarpeshkar and Martin Rinard. June 2016. PLDI 2016. 2. Time Dilation and Contraction for Programmable Analog Devices with Jaunt. Sara Achour and Martin Rinard. December 2017. ASPLOS 2018.

BACKGROUND

BACKGROUND 17

Compiler

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

Dynamical
 System Analog Device

BACKGROUND 18

Compiler

Analog Device Specification Dynamical
 System

BACKGROUND 19

Compiler

Analog Device Specification Dynamical
 System Analog Device Configuration

BACKGROUND 20

Compiler

Analog Device Specification Dynamical
 System Analog Device Configuration

BACKGROUND 21

DYNAMICAL SYSTEM SPECIFICATION · ES = 10−4 ⋅ E ⋅ S − 10−2 ⋅ ES E = 6800 − ES S = 4400 − ES ES(0) = 0

BACKGROUND 22

Compiler

Analog Device Specification Dynamical
 System Analog Device Configuration

BACKGROUND 23

ANALOG DEVICE SPECIFICATION

IADD

x 3

MM

x 3

ADC

x 5

DAC

x 5

BACKGROUND 24

ANALOG DEVICE SPECIFICATION

MM

x 3

inp X0, Y0, Z0 inp A, B

• ut X, Y, Z

Input and Output Ports

BACKGROUND 25

ANALOG DEVICE SPECIFICATION

MM

x 3

inp X0, Y0, Z0 inp A, B

• ut X, Y, Z

rel X.I = X0.I - Z.I rel Y.I = Y0.I - Z.I rel Z.I’ = A.V X.I Y.I - B.V Z.I and Z.I(0) = Z0 Block Dynamics

BACKGROUND 26

ANALOG DEVICE SPECIFICATION

DAC

x 5

ADC

x 5

inp X digital

• ut Z

inp X

• ut Z digital

rel Z.I = X rel Z = X.I

BACKGROUND 27

ANALOG DEVICE SPECIFICATION

IADD

x 3

MM

x 3

ADC

x 5

DAC

x 5

conn MM[*].Z and ADC[*].X conn DAC[*].Z and MM[*].A conn MM[1].Z and MM[2].X Available Connections

BACKGROUND 28

Compiler

Analog Device Specification Dynamical
 System Analog Device Configuration

BACKGROUND 29

ANALOG DEVICE CONFIGURATION

DAC 1 ADC 2 ADC 3 ADC 4 DAC 2 DAC 3 DAC 5 DAC 4 mm.1 X0 Z0 Y0 A B X Z Y ADC 1 ADC 5 iadd.1 B A D C iadd.2 B A D C iadd.3 B A D C

BACKGROUND 30

ANALOG DEVICE CONFIGURATION

DAC 1 ADC 2 ADC 3 ADC 4 DAC 2 DAC 3 DAC 5 DAC 4 mm.1 X0 Z0 Y0 A B X Z Y ADC 1 ADC 5 iadd.1 B A D C iadd.2 B A D C iadd.3 B A D C 0.0001 6800 4400 0.01

BACKGROUND 31

ANALOG DEVICE CONFIGURATION

DAC 1 ADC 2 ADC 3 ADC 4 DAC 2 DAC 3 DAC 5 DAC 4 mm.1 X0 Z0 Y0 A B X Z Y ADC 1 ADC 5 iadd.1 B A D C iadd.2 B A D C iadd.3 B A D C 0.0001 6800 4400 0.01

BACKGROUND 32

ANALOG DEVICE CONFIGURATION

DAC 1 ADC 2 ADC 3 ADC 4 DAC 2 DAC 3 DAC 5 DAC 4 mm.1 X0 Z0 Y0 A B X Z Y ADC 1 ADC 5 iadd.1 B A D C iadd.2 B A D C iadd.3 B A D C 0.0001 6800 4400 0.01 S E ES

BACKGROUND 33

ANALOG DEVICE CONFIGURATION

DAC 1 ADC 1 mm ADC 2 ADC 3 DAC 2 DAC 3 DAC 5 DAC 4 X0 Z0 Y0 A B X Z Y S E ES 0.0001 6800 4400 0.01

BACKGROUND 34

ANALOG DEVICE CONFIGURATION

set DAC[0].X = 0.003 set DAC[5].X = 0.006 … DAC Values

BACKGROUND 35

ANALOG DEVICE CONFIGURATION

set DAC[0].X = 0.003 set DAC[5].X = 0.006 … lbl ADC[0].Z = “E” lbl ADC[1].Z = “S” lbl ADC[2].Z = “ES” ADC Values

BACKGROUND 36

ANALOG DEVICE CONFIGURATION

set DAC[0].X = 0.003 set DAC[5].X = 0.006 … lbl ADC[0].Z = “E” lbl ADC[1].Z = “S” lbl ADC[2].Z = “ES” conn MM[0].Y to ADC[2].X conn MM[0].Z to ADC[3].X conn DAC[0].Z to MM[0].X0 … Connections

BACKGROUND 37

Compiler

Analog Device Specification Dynamical
 System Analog Device Configuration

OUTLINE 38

• Background: overview of compilation problem
• Arco Compiler1: automatically configure analog devices to simulate

dynamical systems.

• Jaunt Solver2: automatically scales dynamical systems to execute

analog hardware with operating range constraints.

• Closing Remarks

TALK OUTLINE

1. Configuration Synthesis for Programmable Analog Devices with Arco. Sara Achour, Rahul Sarpeshkar and Martin Rinard. June 2016. PLDI 2016. 2. Time Dilation and Contraction for Programmable Analog Devices with Jaunt. Sara Achour and Martin Rinard. December 2017. ASPLOS 2018.

ARCO COMPILER

ARCO COMPILER 40

ARCO COMPILER OVERVIEW

Arco performs a search over tableaus

ARCO COMPILER 41

ARCO COMPILER

tableau : search state

{ }

Blocks Goals Wires Config Used Blocks

ARCO COMPILER 42

ARCO COMPILER OVERVIEW

Arco starts with an initial tableau

ARCO COMPILER 43

ARCO COMPILER

initial tableau : the initial state of the search

{ }

Blocks Goals Wires Config Used Blocks

ARCO COMPILER 44

ARCO COMPILER

initial tableau : the initial state of the search

{ }

Blocks Goals Wires Config Used Blocks

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

ARCO COMPILER 45

ARCO COMPILER

initial tableau : the initial state of the search

{ }

Blocks Goals Wires Config Used Blocks

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

DAC[0] ADC[0] MM[0] DAC[1]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X

ARCO COMPILER 46

ARCO COMPILER

initial tableau : the initial state of the search

{ }

Blocks Goals Wires Config Used Blocks

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

DAC[0] ADC[0] MM[0] DAC[1]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X

∅ ∅

analog hardware is not configured yet

ARCO COMPILER 47

ARCO COMPILER OVERVIEW

new tableaus derived using transition rules

ARCO COMPILER 48

ARCO COMPILER OVERVIEW

Arco searches until a solved tableau is found

ARCO COMPILER 49

ARCO COMPILER

solved tableau : the final state of the search

{ }

Blocks Goals Wires Config Used Blocks

ARCO COMPILER 50

ARCO COMPILER

solved tableau : the final state of the search

{ }

Blocks Goals Wires Config Used Blocks

∅

no goals left

ARCO COMPILER 51

ARCO COMPILER

solved tableau : the final state of the search

{ }

Blocks Goals Wires Config Used Blocks DAC[0] . O MM[0] . X0 MM[0] . X ADC[0] . X

∅

ADC[3] ADC[4]

remaining blocks, wires

ARCO COMPILER 52

ARCO COMPILER

solved tableau : the final state of the search

{ }

Blocks Goals Wires Config Used Blocks

ADC[0]

DAC[0] . O MM[0] . X0 MM[0] . X ADC[0] . X

∅

MM[0] DAC[0] ADC[3] ADC[1] ADC[4]

blocks in use

ARCO COMPILER 53

ARCO COMPILER

solved tableau : the final state of the search

{ }

Blocks Goals Wires Config Used Blocks

ADC[0]

DAC[0] . O MM[0] . X0 MM[0] . X ADC[0] . X

∅

MM[0] DAC[0] ADC[3] ADC[1] ADC[4]

set DAC[0].X = 10-4 lbl ADC[2].O = “ES” conn DAC[0].Z 
 to MM[0].A conn MM[0].Z 
 to ADC[0].X

analog device configuration

ARCO COMPILER 54

ARCO COMPILER OVERVIEW

Arco derives new tableaus using transition rules Unify Connect Variable Map

ARCO COMPILER 55

ARCO COMPILER OVERVIEW

Arco derives new tableaus using transition rules Unify Connect Variable Map

ARCO COMPILER 56

{ }

Blocks Goals Wires Config Used Blocks

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

DAC[0] ADC[0] MM[0] DAC[1]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X

E = 6800 − ES UNIFICATION TRANSITION

ARCO COMPILER 57

Goals

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

Blocks

MM[0]

UNIFICATION TRANSITION

ARCO COMPILER 58

Goals

E = 6800 − ES

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

MM[0]

ARCO COMPILER 59

Goals

E = 6800 − ES

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

X = X0 − Z

MM[0]

ARCO COMPILER 60

Goals

E = 6800 − ES

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

X = X0 − Z

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

MM[0]

ARCO COMPILER 61

Goals

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

· ES = 10−4E ⋅ S − 10−2ES ES(0) = 0 · Z = A ⋅ X ⋅ Y − B ⋅ Z Z(0) = Z0

MM[0]

ARCO COMPILER 62

Goals

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

· ES = 10−4E ⋅ S − 10−2ES ES(0) = 0 · ES = A ⋅ E ⋅ Y − B ⋅ ES ES(0) = Z0 ES E ES ES

MM[0]

ARCO COMPILER 63

Goals

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

· ES = 10−4E ⋅ S − 10−2ES ES(0) = 0 · ES = A ⋅ E ⋅ Y − B ⋅ ES ES(0) = Z0 ES E ES ES

S

10−4 10−2

MM[0] . A = 10−4 MM[0] . B = 10−2 MM[0] . Y = S MM[0] . Z0 = 0

MM[0]

ARCO COMPILER 64

Goals

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

S

10−4 10−2

MM[0] . A = 10−4 MM[0] . B = 10−2 MM[0] . Y = S MM[0] . Z0 = 0

S = 4400 − ES S = Y0 − ES ES S

MM[0]

ARCO COMPILER 65

Goals

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

S

10−4 10−2

MM[0] . A = 10−4 MM[0] . B = 10−2 MM[0] . Y = S MM[0] . Z0 = 0

S = 4400 − ES S = Y0 − ES ES S

4400

MM[0] . Y0 = 4400

MM[0]

ARCO COMPILER 66

Goals

mm X0 Z0 Y0 A B X Z Y

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

E 6800 ES

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

S

10−4 10−2

MM[0] . A = 10−4 MM[0] . B = 10−2 MM[0] . Y = S MM[0] . Z0 = 0

S = 4400 − ES S = Y0 − ES ES S

4400

MM[0] . Y0 = 4400

MM[0]

ARCO COMPILER 67

{ }

Blocks Goals Wires Config Used Blocks

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

DAC[0] ADC[0] MM[0] DAC[1]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X

UNIFICATION TRANSITION

ARCO COMPILER 68

{ }

Blocks Goals Wires Config Used Blocks

· ES = 10−4E ⋅ S − 10−2ES E = 6800 − ES S = 4400 − ES ES(0) = 0

DAC[0] ADC[0] DAC[1]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X

MM[0] . X0 = 6800 MM[0] . X = E MM[0] . Z = ES

MM[0] MM[0]

′

UNIFICATION TRANSITION

ARCO COMPILER 69

ARCO COMPILER OVERVIEW

Arco derives new tableaus using transition rules Unify Connect Variable Map

ARCO COMPILER 70

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

DAC[0] . X = 10−4 ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

CONNECTION TRANSITION

ARCO COMPILER 71

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

DAC[0] . X = 10−4 ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

CONNECTION TRANSITION

ARCO COMPILER 72

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . A DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

DAC[0] . X = 10−4 ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

conn DAC[0].Z 
 to MM[0].A

′

CONNECTION TRANSITION

ARCO COMPILER 73

ARCO COMPILER OVERVIEW

Arco derives new tableaus using transition rules Unify Connect Variable Map

ARCO COMPILER 74

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

DAC[0] . X = 10−4 ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

conn DAC[0].Z 
 to MM[0].A MM[0] . Y ADC[0] . X

VARIABLE/VALUE MAPPING TRANSITION

ARCO COMPILER 75

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

DAC[0] . X = 10−4 ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

conn DAC[0].Z 
 to MM[0].A MM[0] . Y ADC[0] . X set DAC[0].X = 10-4

′

VARIABLE/VALUE MAPPING TRANSITION

ARCO COMPILER 76

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

conn DAC[0].Z 
 to MM[0].A MM[0] . Y ADC[0] . X

VARIABLE/VALUE MAPPING TRANSITION

DAC[0] . X = 10−4 set DAC[0].X = 10-4

ARCO COMPILER 77

{ }

Blocks Goals Wires Config Used Blocks

MM[1] MM[2] ADC[3]

DAC[0] . O MM[0] . X0 MM[0] . Z ADC[0] . X MM[0] . X ADC[0] . X MM[0] . A = DAC[0] . O

MM[0]

DAC[0] . X = 10−4 ADC[0] . X = MM[0] . Z ADC[0] . O = ES MM[0] . B = DAC[0] . O DAC[0] . X = 10−2 ADC[1] . X = MM[0] . X ADC[1] . O = E

DAC[0] DAC[1] ADC[0] ADC[1] ADC[4]

conn DAC[0].Z 
 to MM[0].A MM[0] . Y ADC[0] . X set DAC[0].X = 10-4

′

VARIABLE/VALUE MAPPING TRANSITION

lbl ADC[0].O = ES

ARCO COMPILER 78

ARCO COMPILER RECAP

Arco starts with an initial tableau

ARCO COMPILER 79

ARCO COMPILER RECAP

derives new tableaus using transition rules Unify Connect Variable Map

ARCO COMPILER 80

ARCO COMPILER RECAP

until a solved tableau is found

ARCO COMPILER 81

ARCO COMPILER RECAP

analog device configuration in solved tableau

ARCO COMPILER 82

ARCO COMPILER RECAP

analog device configuration in solved tableau

ALGEBRAICALLY EQUIVALENT TO DYNAMICAL SYSTEM

creative use of available analog blocks to model dynamics respects connectivity, block instance constraints

TEXT 83

CASE STUDY 1: PERK-4

iadd

O = A + B + C

O A B C

switch

O S K M n

O = M (S ⋅ K−1 + 1)n

• 1

PERK 4 1 1 PERK-4

O = M ((A + B + C) ⋅ K−1 + 1)n O = 1 ((PERK + (−1) + 0) ⋅ 1−1 + 1)4

PERK-4

Task: model PERK-4 using analog hardware that does not directly support exponentiation.

ARCO COMPILER 84

ARCO COMPILER RECAP

analog device configuration in solved tableau doesn’t take into consideration

PHYSICAL LIMITATIONS OF HARDWARE

ARCO COMPILER 85

ARCO COMPILER RECAP

analog device configuration in solved tableau doesn’t take into consideration

PHYSICAL LIMITATIONS OF HARDWARE

OPERATING RANGE CONSTRAINTS SAMPLING RATES OF ADCS/DACS

BACKGROUND 86

ANALOG DEVICE CONFIGURATION REVISITED

DAC1 ADC1

mm

ADC2 ADC3 DAC2 DAC3 DAC5 DAC4 X0 A X Z Y B Y0 Z0

S E ES 0.0001 6800 4400 0.01

DAC1 ADC1

mm

ADC2 ADC3 DAC2 DAC3 DAC5 DAC4 X0 A X Z Y B Y0 Z0

S E ES 0.0001 6800 4400 0.01

BACKGROUND 87

ANALOG DEVICE CONFIGURATION REVISITED

2 4 6 8 10 time (su) 2000 4000 6000 molecules

Expected Simulation Dynamics

BACKGROUND 88

ANALOG DEVICE CONFIGURATION REVISITED

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

S E ES 0.0001 6800 4400 0.01

BACKGROUND 89

ANALOG DEVICE CONFIGURATION REVISITED

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

DAC2

[0,3300]

DAC4

[0,3300]

S E ES 0.0001 6800 4400 0.01

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

DAC2

[0,3300]

DAC4

[0,3300]

S E ES 0.0001 6800 4400 0.01

BACKGROUND 90

ANALOG DEVICE CONFIGURATION REVISITED

2 4 6 8 10 time (su) 2000 4000 6000 molecules

2 4 6 8 10 time (su) 2000 4000 6000 molecules

Actual Simulation Dynamics

BACKGROUND 91

UNIFORMLY SCALED ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

a15•S a13•E a14•ES 0.1•10-4 0.1•6800 0.1• 0.1•4400 0.1•10-2

BACKGROUND 92

UNIFORMLY SCALED ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

a15•S a13•E a14•ES 0.1•10-4 0.1•6800 0.1• 0.1•4400 0.1•10-2

DOES NOT WORK!

BACKGROUND 93

UNIFORMLY SCALED ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

a15•S a13•E a14•ES 0.1•10-4 0.1•6800 0.1• 0.1•4400 0.1•10-2

DOES NOT WORK!

SCALED SIGNAL CHANGES SIMULATION ORIGINAL SIMULATION NOT RECOVERABLE

OUTLINE 94

• Background: overview of compilation problem
• Arco Compiler1: automatically configure analog devices to simulate

dynamical systems.

• Jaunt Solver2: automatically scales dynamical systems to execute

analog hardware with operating range constraints.

• Closing Remarks

TALK OUTLINE

1. Configuration Synthesis for Programmable Analog Devices with Arco. Sara Achour, Rahul Sarpeshkar and Martin Rinard. June 2016. PLDI 2016. 2. Time Dilation and Contraction for Programmable Analog Devices with Jaunt. Sara Achour and Martin Rinard. December 2017. ASPLOS 2018.

JAUNT SOLVER

BACKGROUND 96

Jaunt

Analog Device Specification Scaled Analog Device Configuration Analog Device Configuration

BACKGROUND 97

Jaunt

Analog Device Specification Analog Device Configuration Scaled Analog Device Configuration physically realizable: signals within port operating ranges recoverable: recover original simulation at ADCs

BACKGROUND 98

ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

X0

[0,1000]

A

[10-5,10-3] [0,1600]

X

[0,1600]

Z

[0,1600]

Y B

[10-4,1]

Y0

[0,1000]

Z0

[0,1000]

S E ES 10-4 6800 4400 10-2

BACKGROUND 99

SCALED ANALOG DEVICE CONFIGURATION

mm

DAC1

[0,10]

ADC1

[0,3300]

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a16•S a14•E a15•ES a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

τ

simulation speed

BACKGROUND 100

SCALED ANALOG DEVICE CONFIGURATION

mm

DAC1

[0,10]

ADC1

[0,3300]

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a16•S a14•E a15•ES a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

τ

simulation speed

BACKGROUND 101

SCALED ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a16•S a14•E a15•ES a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

τ

simulation speed

BACKGROUND 102

SCALED ANALOG DEVICE CONFIGURATION

τ

simulation speed

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a16•S a14•E a15•ES a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

multiply parameters by scaling factors

BACKGROUND 103

SCALED ANALOG DEVICE CONFIGURATION

τ

simulation speed

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a16•S a14•E a15•ES a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

physically realizable: signals in port operating ranges

BACKGROUND 104

SCALED ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a10•X

[0,1600]

a11•Z

[0,1600]

a12•Y a9•B

[10-4,1]

a8•Y0

[0,1000]

a8•Z0

[0,1000]

a15•S a13•E a14•ES a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

τ

simulation speed

• Recover Simulation:
• divide ADC samples by a13-a15
• multiply hardware time by τ

BACKGROUND 105

JAUNT SOLVER

• Objective: Find numerical assignments for scaling

factors that produces fastest simulation

• Scaling Factors: τ,a1, …, a15
• Values: real numbers > 0

BACKGROUND 106

JAUNT SOLVER

• Objective: Find numerical assignments for scaling

factors that produces fastest simulation

• Scaling Factors: τ,a1, …, a15
• Values: real numbers > 0
• Geometric Program: Convex optimization problem
• Device Configuration → Geometric Program

∏

TEXT 107

• Maximize τ subject to:
• Factor Constraints
• Sampling Constraints
• Connection Constraints
• Operating Range Constraints

GEOMETRIC PROGRAM GENERATION

∏

TEXT 108

• Maximize τ subject to:
• Factor Constraints
• Sampling Constraints
• Connection Constraints
• Operating Range Constraints

GEOMETRIC PROGRAM GENERATION

∏

given block with scaled input signals: → original output signal is recoverable from scaled output signal

TEXT 109

FACTOR CONSTRAINTS

mm

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

τ

simulation speed

a12 ⋅ Z = ∫ [a6a11a13 ⋅ A ⋅ X ⋅ Y − a9a12 ⋅ B ⋅ Z]τ−1 ⋅ dt a6a11a13 a9a12 τ−1 a12

TEXT 110

FACTOR CONSTRAINTS

mm

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

τ

simulation speed

a12 ⋅ Z = ∫ a6a11a13 ⋅ [A ⋅ X ⋅ Y − ⋅B ⋅ Z]τ−1 ⋅ dt a6a11a13 = a9a12 τ−1 a12 a6a11a13

TEXT 111

FACTOR CONSTRAINTS

mm

a7•X0

[0,1000]

a6•A

[10-5,10-3] [0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

τ

simulation speed

a6a11a13τ−1[Z = ∫ ⋅ [A ⋅ X ⋅ Y − ⋅B ⋅ Z] ⋅ dt] a6a11a13τ−1 a6a11a13τ−1 = a12 a6a11a13 = a9a12

TEXT 112

• Maximize τ subject to:
• Factor Constraints
• Sampling Constraints
• Connection Constraints
• Operating Range Constraints

GEOMETRIC PROGRAM GENERATION

∏

given DAC/ADC: → ensure simulation is executed slowly enough for adequate sampling

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

[0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y

a16•S a14•E a15•ES

BACKGROUND 113

SAMPLE CONSTRAINTS

simulation speed

1 sample/hu 1 sample/hu 1 sample/hu

2 sample/su ≤ 1 sample/hu ⋅ τ−1 τ−1 τ : hu → su τ

minimum number of samples / simulation time unit

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

[0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y

a16•S a14•E a15•ES

BACKGROUND 114

SAMPLE CONSTRAINTS

simulation speed

1 sample/hu 1 sample/hu 1 sample/hu

2 sample/su ≤ 1 sample/hu ⋅ τ−1 τ−1 τ : hu → su τ

number of samples in one hardware time unit

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

[0,1600]

a11•X

[0,1600]

a12•Z

[0,1600]

a13•Y

a16•S a14•E a15•ES

BACKGROUND 115

SAMPLE CONSTRAINTS

simulation speed

1 sample/hu 1 sample/hu 1 sample/hu

2 sample/su ≤ 1 sample/hu ⋅ τ−1 τ−1 τ : hu → su τ

number of samples in one hardware time unit

τ−1 : hu su

TEXT 116

• Maximize τ subject to:
• Factor Constraints
• Sampling Constraints
• Connection Constraints
• Operating Range Constraints

GEOMETRIC PROGRAM GENERATION

∏

given a connection: → ensure signal is scaled equally on both sides of connection

BACKGROUND 117

CONNECTION CONSTRAINTS

DAC1

[0,10]

mm

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3]

a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

a1 = a6 a2 = a7 a3 = a8 a1 a2 a3 a7 a6 a8

TEXT 118

• Maximize τ subject to:
• Factor Constraints
• Sampling Constraints
• Connection Constraints
• Operating Range Constraints

GEOMETRIC PROGRAM GENERATION

∏

given an input/output port: → ensure signal stays within the operating range of the port

BACKGROUND 119

OPERATING RANGE RANGE CONSTRAINTS

DAC1

[0,10]

mm

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

a7•X0

[0,1000]

a6•A

[10-5,10-3]

a10•B

[10-4,1]

a9•Y0

[0,1000]

a8•Z0

[0,1000]

a1•10-4 a2•6800 a3•0 a4•4400 a5•10-2

0 ≤ a7 ⋅ 6800 ≤ 1000

TEXT 120

• Maximize τ subject to:
• Factor Constraints
• Sampling Constraints
• Connection Constraints
• Operating Range Constraints

GEOMETRIC PROGRAM GENERATION

∏

TEXT 121

GEOMETRIC PROGRAM GENERATION

∏

GEOMETRIC PROGRAMMING LIBRARY CONVERT TO CONVEX PROGRAM CONVEX SOLVER [CVXOPT]

Scaled Analog Device Configuration

Geometric Program

BACKGROUND 122

SCALED ANALOG DEVICE CONFIGURATION

DAC1

[0,10]

ADC1

[0,3300]

mm

ADC2

[0,3300]

ADC3

[0,3300]

DAC2

[0,3300]

DAC3

[0,3300]

DAC5

[0,10]

DAC4

[0,3300]

0.06•X0

[0,1000]

8.28•A

[10-5,10-3] [0,1600]

0.06•X

[0,1600]

0.06•Z

[0,1600]

0.06•Y 0.5•B

[10-4,1]

0.06•Y0

[0,1000]

0.06•Z0

[0,1000]

0.06•S 0.06•E 0.06•ES 8.28•10-4 0.06•6800 0.06•0 0.06•4400 0.5•10-2

0.5

simulation speed

TEXT 123

CASE STUDY: REPRISSILATOR

200 400 600 800 1000 time (su) 25 50 75 100 125 molecules

gene network that generates oscillations “synthetic genetic clock”

reference simulation

TEXT 124

CASE STUDY: REPRISSILATOR

200 400 600 800 1000 time (su) 25 50 75 100 125 molecules

simulation using unscaled configuration

200 400 600 800 1000 time (su) 50 100 150 molecules

reference simulation simulation without jaunt

saturates, loses oscillations

TEXT 125

CASE STUDY: REPRISSILATOR

200 400 600 800 1000 time (su) 25 50 75 100 125 molecules

200 400 600 800 1000 time (su) 50 100 150 molecules

Reference Simulation

100 200 300 time (hu) 200 400 600 800 1000 signal

simulation with jaunt before recovery

simulation using scaled configuration executes 2.839x faster than unscaled configuration

TEXT 126

CASE STUDY: REPRISSILATOR

200 400 600 800 1000 time (su) 25 50 75 100 125 molecules

200 400 600 800 1000 time (su) 50 100 150 molecules

Reference Simulation simulation with jaunt after recovery

200 400 600 800 1000 time (su) 25 50 75 100 125 molecules

simulation using scaled configuration scaling samples and time recovers original simulation

OUTLINE 127

• Background: overview of compilation problem
• Arco Compiler1: automatically configure analog devices to simulate

dynamical systems.

• Jaunt Solver2: automatically scales dynamical systems to execute

analog hardware with operating range constraints.

• Closing Remarks

TALK OUTLINE

1. Configuration Synthesis for Programmable Analog Devices with Arco. Sara Achour, Rahul Sarpeshkar and Martin Rinard. June 2016. PLDI 2016. 2. Time Dilation and Contraction for Programmable Analog Devices with Jaunt. Sara Achour and Martin Rinard. December 2017. ASPLOS 2018.

WHAT NEXT?

CLOSING REMARKS 129

SENDYNE HYBRID DIGITAL-ANALOG COMPUTATION CHIP

TEXT

WHAT IS THE DIFFERENCE BETWEEN THESE CIRCUITS?

130

CURRENT MIRROR CONSTANT GAIN (2) CURRENT MULT LUT F(X) = 2X

X X X X

NO-CLK DAC NO-CLK ADC

2X 2X 2X 2 2X

TEXT

WHAT IS THE DIFFERENCE BETWEEN THESE CIRCUITS?

131

CURRENT MIRROR CONSTANT GAIN (2) CURRENT MULT LUT F(X) = 2X

X X X X

NO-CLK DAC NO-CLK ADC

2X 2X 2X 2 2X

NOISE BEHAVIOR! HIGH NOISE LOW NOISE

TEXT

WHAT IS THE DIFFERENCE BETWEEN THESE CIRCUITS?

132

CURRENT MIRROR CONSTANT GAIN (2) CURRENT MULT LUT F(X) = 2X

X X X X

NO-CLK DAC NO-CLK ADC

2X 2X 2X 2 2X

NOISE BEHAVIOR! HIGH NOISE LOW NOISE

IS THIS BAD?

TEXT 133

IS THIS BAD?

inherent variance in physical systems SDES circuit noise = stochastic behavior

• ther stochastic processes

TEXT 134

IS THIS BAD?

uncertainty in modeling physical systems unmodeled dynamics empirically derived models circuit noise <= uncertainty

TEXT

TECHNIQUES FOR MANIPULATING NOISE

135

Option 1: Rearrange circuit to reduce noise

CURRENT MULT

X Y

CURRENT MIRROR

2XY

CURRENT MULT

X Y

CURRENT MIRROR

2XY 2X

[ noise-aware circuit generation ]

Noise Signal

TEXT

TECHNIQUES FOR MANIPULATING NOISE

136

CURRENT MIRROR

a1X 2a1X

Option 2: Increase dynamic range of X

CURRENT MIRROR

X 2X

[ noise-aware parameter scaling ]

Noise Signal

TEXT

TECHNIQUES FOR MANIPULATING NOISE

137

CURRENT MIRROR

X 2X

Option 3: Insert filter that removes noise

CURRENT MIRROR

X 2X

LPF

[ automated filter configuration ]

ω ω ω Noise Signal

TEXT

WHAT NEXT?

138

Legno: noise-aware configuration generation noise-aware scaling transforms ranked configuration generation automated filter generation

BACKGROUND 139

Legno

Analog Device Specification Stochastic
 Differential Equations Analog Device Configuration

+

Analytical 
 Noise Model

BACKUP SLIDES

CLOSING REMARKS

SARPSHKAR GROUP PROTEIN CHIP

141

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Fig. 1. Poisson chemical reaction flux and Poisson electron flow in

• n multi-chip electronic boards [13]. Therefore, we were moti-

• Fig. 2. Die micrograph of the

• f one gene block (2x magnification).

• ther via digital input/output (I/O), and with off-chip dig-

• r to a computer. For simplicity, the data in this paper were

• Frontier (F): Tableau

configurations to explore

• choose: chooses the

tableau t in F to explore.

• select: chooses the set of

transitions to apply to t

Algorithm: F = initial tableau while F, choose t in F: if t is terminal return Z

• therwise:

select T: set of t’ where t→t’ remove t from F, add T to F

The Search Algorithm

142

• Search Heuristics
• choose lowest

complexity tableau configuration.

• select a simple

goal, and prioritize transitions that solve it.

Algorithm: F = initial tableau while F, choose t in F: if t is terminal return Z

• therwise:

select T: set of t’ where t→t’ remove t from F, add T to F

Search Optimizations

143

• Component Aggregation: aggregate instances of

the same component

• Pro: smaller search space
• Con: instance constraints must be handled

separately

• Partial Configuration Caching
• Compact Search Tree Data Structure

Search Optimizations

144

• 1. Transitions Over Tableau

b { | h

unify

r 2 R [ ˙ R e r 2 e R

unify(r,e

r, R, ˙ R, e R) = hR

0, ˙

R0, e R

0i

hR, ˙ R, W, e R, Zi ! hR

0, ˙

R0, W, e R

0, Zi

145

• 1. Transitions Over Tableau

b ;i ! ⇤ h ; i}

connect

e r : iq = oq 2 e R w : ho, ii 2 W hR, ˙ R, W, e R, Zi ! hR, ˙ R, W {w}, e R { e r}, Z [ {o i}i

• 146

• 1. Transitions Over Tableau
• e

e e e e h e i ! h e i

input-var-map

e r : id =b i 2 e R b i 2b I i @ c c 2 IC hR, ˙ R, W, e R, Zi ! hR, ˙ R, W, e R { e r}, Z [ { b i 7! id}i

147

Geometric Programming Problem

monomial mi

2 mi = ci xi,τ Y

p 2P

axi,p

p

mi  1,i = 1, ...,n sj = 1, j = 1, ...,m Here the are

• f the following form,

j

2 minimize sopt

posynomial pi

si = X

i

The variables in a geometric

i i i =

X

i

ci xi,τ Y

p 2P

axi,p

p

in a geometric program (i.e., ) take

Analog Hardware Components

Component Quantity Description iin 25 current input vin 125 voltage input

• uti

10 current output vout 75 voltage output vgain 40 voltage gain iadd 30 current adder vadd 35 voltage adder vtoi 30 voltage to current converter itov 30 current to voltage converter ihill 8 hill function for activation/repression igenebind 8 gene binding switch 15 genetic switch mm 2 Michaelis-Menten dynamics Relation ZI = XD ZV = XD ZD = XI ZD = XV OV = (XV · ZV)/(YV · 25) OI = AI + BI + CI + DI capacitor ∂O2V/∂t = 0.1(AV + BV − CV − DV · O2V) O1V = 0.1(AV + BV − CV − DV) OI = XV/KV OI = KV · XI SI = MV(SI/KI)nV/((SI/KI)nV + 1) RI = MV/((SI/KI)nV + 1) OI = MI/(1 + KI · TI) OI = MI/(SI/KI + 1)nV XV = XtV − XYV YV = YtV − XYV ∂XYV/∂t = KI · XV · YV − RI · XYV

selection of analog components from collaborators, textbooks and publications


• G. Cowan, R. Melville, and Y. Tsividis. A VLSI analog computer/digital computer accelerator. Solid-State Circuits, IEEE Journal of, 41(1):42–53, Jan 2006. ISSN 0018-9200. doi: 10.1109/

• R. Daniel, S. S. Woo, L. Turicchia, and R. Sarpeshkar. Analog transistor models of bacterial genetic circuits. In Biomedical Circuits and Systems Conference (BioCAS), 2011 IEEE, IEEE, 2011.
• R. Sarpeshkar. Ultra Low Power Bioelectronics: Funda- mentals, Biomedical Applications, and Bio-Inspired Systems. Cambridge University Press, 2010. ISBN 0521857279.
• J. J. Y. Teo, S. S. Woo, and R. Sarpeshkar. Synthetic biology: A unifying view and review using analog circuits. IEEE Trans. Biomed. Circuits and Systems, 9(4):453–474, 2015.
• S. S. Woo, J. Kim, and R. Sarpeshkar. A cytomorphic chip for quantitative modeling of fundamental bio-molecular circuits. IEEE Trans. Biomed. Circuits and Systems, 9(4):527–542, 2015.

149

• menten: Michaelis-Menten equation reaction. D. R. F. PhD. Biochemistry (Lippincott Illustrated Reviews Series). LWW, 2013. ISBN

• gentoggle: genetic toggle switch in E.col. T. S. Gardner, C. R. Cantor, and J. J. Collins. Construction of a genetic toggle switch in

• repri: synthetic oscillatory network of transcriptional regulators. M. B. Elowitz and S. Leibler. A synthetic oscillatory network of

• osc: circadian oscillation utilizing activator / repressor. J. M. Vilar, H. Y. Kueh, N. Barkai, and S. Leibler. Mechanisms of noise-

• apop: protein stress response. K. Erguler, M. Pieri, and C. Deltas. A mathematical model of the unfolded protein stress response

Dynamical Systems Benchmarks

Benchmark Parameters Functions Differential Equations menten 3 4 gentoggle 9 3 2 repr 7 3 6

• sc

16 16 9 apop 87 48 27 [11]

selection of published artifacts from well- cited computational biology papers from Biomodels database 


150

Components

Fraction of each Component 0% 25% 50% 75% 100% menten gtoggle repri

• sc

apop

vgain vadd mm vtoi itov iadd switch ihill igenebind

151

Arco Runtime

Number of Equations 20 40 60 80 menten gentoggle repri

• sc

apop Runtime (m) 15 30 45 60 menten gentoggle repri

• sc

apop

152

Geometric Programming Problem

monomial mi

2 mi = ci xi,τ Y

p 2P

axi,p

p

mi  1,i = 1, ...,n sj = 1, j = 1, ...,m Here the are

• f the following form,

j

2 minimize sopt

posynomial pi

si = X

i

The variables in a geometric

i i i =

X

i

ci xi,τ Y

p 2P

axi,p

p

in a geometric program (i.e., ) take

benchmark speedup No Jaunt Jaunt

smol

0.50x

✓

sconc

1.00x

✓

mmrxnp

77.48x

✓

repri

2.839x

✓

bont

5.00x

✓* ✓

epor

0.142x

✓

gtoggle

0.1x

✓

Correctness+Speedup Results

Simulation Speed Analysis

155

Jaunt Execution Times

156