Preparing for a Post Moores Law World Todd Austin University of - - PowerPoint PPT Presentation

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Preparing for a Post Moores Law World Todd Austin University of - - PowerPoint PPT Presentation

Sep 26, 2023 188 likes •598 views

Preparing for a Post Moores Law World Todd Austin University of Michigan Perspectives on Scaling C-FAR : Center for Future Architectures Research Focused on scaling in 2020-2030 silicon Performance, power and cost 27 faculty

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Preparing for a Post Moore’s Law World

Todd Austin University of Michigan

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Perspectives on Scaling

  • C-FAR: Center for Future Architectures Research
  • Focused on scaling in 2020-2030 silicon
  • Performance, power and cost
  • 27 faculty at 14 universities, 92 students
  • Why is C-FAR’s mission important?
  • The promise… tomorrow’s applications need powerful systems
  • Why is C-FAR’s mission challenging?
  • The threats… slowing innovation and degrading silicon

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Computer Vision Machine Learning Big Data Analytics End of Dennard Scaling Many Idle Cores Silicon Defects

All of the work presented in this talk is that of C-FAR faculty.

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Moore’s Law Performance Gap

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Today, gap is cresting 10x Lack of perceived value Dark silicon Diminished ILP

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180 130 90 65 45 32 22 14 10 7 1 10 100 1000 Technology Node (nm) 10nm slips by 5-6 quarters 14nm slips by 2 quarters 7nm by end 2020?

Is Density Still Scaling?

Street Dates for Intel’s Lead Generation Products

Courtesy David Brooks @ Harvard 4

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But, the technology scaling component has left us.

What Does This All Mean to Architects?

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Today, value = scalability (performance, power, cost).

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Remedy #1: Chip Multiprocessors

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CMP Performance Scaling for the Highly Parallel PARSEC Benchmarks

7 From “Dark Silicon and the End of Multicore Scaling,” by Esmaeilzadeh et al.

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What Does the Press Think?

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We Investigate: Who’s to Blame?

9

?

Programmers

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Largest NA Bitcoin Miner

  • GPGPU-based system
  • Fills 2000 sq.ft. warehouse
  • Computes 1 petahash/s
  • Reportedly generates $8M

in Bitcoins per month

  • Unfortunately soon to be
  • bsolete as Bitcoin difficulty

continues to scale

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We Investigate: Who’s to Blame?

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?

Programmers Educators

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CS Education is Booming

  • CS enrollment on a fast-rising trajectory for a decade
  • Parallel programming at UM
  • EECS 381, Object-Oriented and Advanced Programming
  • EECS 482, Operating Systems
  • EECS 570, Parallel Computer Architecture
  • EECS 587, Parallel Computing
  • EECS 591, Distributed Systems
  • EECS 598, Ubiquitous Parallelism
  • I have been teaching and

developing CS in Ethiopia

  • Nearly 600 students in the

CS program

  • 2nd most popular major in the

university

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CS EE CE

UM EECS Enrollment

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We Investigate: Who’s to Blame?

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?

Programmers Educators The Transistor

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The Dark Silicon Dilemma

14 Courtesy Michael Taylor @ UCSD

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The Dark Silicon Dilemma

15 Courtesy Michael Taylor @ UCSD

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The Dark Silicon Dilemma

16 Courtesy Michael Taylor @ UCSD

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We Investigate: Who’s to Blame?

17

?

Programmers Educators Architects The Transistor

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The Tyranny of Amdahl’s Law

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(P) (N) (S)

Where we need to be today! (10x)

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We Investigate: Who’s to Blame?

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?

Programmers Educators Architects The Transistor What is the solution?

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A Story about Jason and His Two Advisors

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EVA: Embedded Vision Architecture

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Application-specific Functional Units Heterogeneous Multicore EVA Functional Units Monopoly Compare, Dot Product Unit, Vector Max, Decision Tree Compare

Initial EVA design:

90x greater efficiency for computer vision algorithms Customized Memory System

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Where We Need to Focus

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Parallelism Customization

Heterogeneous parallel systems

  • vercome dark silicon and the tyranny of Amdahl’s Law.
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Why These Ideas Will Likely Fail, Unless We Make a Change…

  • The Good: Hetero-parallel systems

can close the Moore’s Law gap

  • The Bad: Dennard scaling has

stopped, Moore’s Law is slowing, leaving a growing gap

  • The Ugly: Hetero-parallel designs

needed to close the gap will be too expensive to afford

  • We must make design much cheaper!

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What I Want You to Remember

  • Successfully bridging the Moore’s Law performance gap is

less about “How” to do it and more about “How Much” does it cost!

  • My claim: if we can effect a 100x reduction in the cost to

bring a design to market, innovation will flourish and scaling challenges will be overcome.

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Design Costs Are Skyrocketing

20 40 60 80 100 120 140 0.5u 0.35u 0.25u 0.18u 0.13u 90nm 65nm 45nm 28nm 20nm Cost to Market ($ million) Silicon Technology Node Mask Costs S/W Development and Testing H/W Design and Verification Source: International Business Strategies

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$88M $120M $500K

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Outcome: “Nanodiversity” is Dwindling

Source: Gartner Group

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2000 4000 6000 8000 10000 12000 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

Total ASIC Starts Year

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Inexpensive “Design” Promotes Innovation and Adaptation

  • Don’t Believe Me? Ask Mother Nature!
  • r/K selection theory is a biological mechanism

that organisms use to better adapt to their environment

  • In unstable environments, r-selection

predominates as the ability to reproduce quickly is crucial

  • In stable environments, K-selection

predominates as the ability to compete successfully for limited resources is crucial

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The Remedy: Scale Innovation

  • Ultimate goal: accelerate system architecture innovation

and make it sufficiently inexpensive that anyone can do it anywhere

  • Approach #1: Expect more from architectural innovation
  • Approach #2: Reduce the cost to design custom hardware
  • Approach #3: Embrace open-source concepts
  • Approach #4: Widen the applicability of custom hardware
  • Approach #5: Reduce the cost of manufacturing custom H/W

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1) Expect more from architectural innovation

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“Give me 15% speedup and I’ll accept your paper” “I need 1% speedup for 1% area” “Your idea needs to deliver 2x or more, or someone else should fund it”

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HELIX-UP Unleashed Parallelization

  • Traditional parallelizing

compilers must honor possible dependencies

  • HELIX-UP manufactures

parallelism by profiling which deps do not exist and which are not needed

  • Based on user supplied output

distortion function

  • Big step for parallelization
  • 2x speedup over parallelizing

compilers, 6x over serial, < 7% distortion

Thread 0 Thread 1 Thread 2 Thread 3

Data Data Data Iteration 0 Iteration 1

David Brooks @ Harvard

Nehalem 6 cores, 2 threads per core 30

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Association Rule Mining with the Automata Processor

  • Micron’s Automata processor
  • Implements FSMs at memory
  • Massively parallel with accelerators
  • Mapped data-mining ARM rules

to memory-based FSMs

  • ARM algorithms identify relationships

between data elements

  • Implementations are often memory

bottlenecked

  • Big-data sets had big speedups
  • 90x+ over single CPU performance
  • 2-9x+ speedups over CMPs and GPUs
  • Joint effort with UVA and Micron

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Kevin Skadron @ UVA

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2) Reduce the cost to design custom hardware

  • Better tools and infrastructure
  • Scalable accelerator synthesis and compilation, generate code and H/W for

highly reusable accelerators

  • Composable design space exploration, enables efficient exploration of

highly complex design spaces

  • Well put-together benchmark suites to drive development efforts

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Shared Memory/Interconnect Models Unmodified C-Code Accelerator Design Parameters (e.g., # FU, mem. BW) Private L1/ Scratchpad Accelerator Specific Datapath

David Brooks @ Harvard

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Feature Tracking Disparity Map Image Stitch Image Segmentation Robot Localization Texture Synthesis SIFT Support Vector Machines

CortexSuite: A Synthetic Brain Benchmark Suite

Michael Taylor @ UCSD

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  • Thought experiment: let’s design the next great

smartphone

3) Embrace Open-Source Concepts

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Red = non-free IP, Green = free IP

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3) Embrace Open-Source Concepts

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As a community, we need to consider: How much of our basic technology should be free?

Red = non-free IP, Green = free IP

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Open-Source H/W is Growing

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4) Widen the Applicability of Customized H/W

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  • ESP: Ensembles of Specialized Processors
  • Ensembles are algorithmic-specific processors optimized for code “patterns”
  • Approach uses composable customization to deliver speed and efficiency

that is widely applicable to general purpose programs

  • Grand challenges remain: what are the components and how are they

connected?

ILP Engine Dense Engine Sparse Engine Graph Engine ESP Core

Glue Code Dense Code Sparse Code Graph Code ESP Code

Dense Graph Sparse

…

Applications

Multimedia Analysis Computer Vision Machine Learning

Computational Patterns Specializers with custom implementations and autotuning Krste Asanovic @ UC-Berkeley

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  • Brick-and-mortar silicon explores assembly-time

customization, i.e., MCMs + 3D + FPGA interconnect

  • Diversity via brick ecosystem & interconnect flexibility
  • Brick design costs amortized across all designs
  • Robust interconnect and custom bricks rival ASIC speeds
  • Another thought experiment: what if building a house

were like fabricating a chip?

5) Reduce the cost of manufacturing customized H/W

H/W brick 38

Martha Kim @ Columbia

Brick-and-mortar silicon design flow: 1) Assemble brick layer 2) Connect with mortar layer 3) Package assembly 4) Deploy software

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Conclusions

  • Heterogeneous design could continue

Moore’s law perf. scaling via innovation alone

  • But, it requires a diverse hardware ecosystem with

affordable customization

  • Effective and affordable customization won’t

happen without our help

1.

Expect more from architectural innovation

2.

Reduce the cost to design customized design

3.

Embrace open-source concepts

4.

Widen the applicability of customization

5.

Reduce the cost of custom manufacturing

  • Increasing “nanodiversity” is a good thing
  • More jobs, companies, and students
  • More competition and scalable innovation

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Questions

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? ? ? ? ? ? ? ? ? ? ?