PPP over SONET from STS-1 (STM-0/AU-3) to STS-192c (STM-64/AU-4-64c) - - PowerPoint PPT Presentation

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PPP over SONET from STS-1 (STM-0/AU-3) to STS-192c (STM-64/AU-4-64c)

<draft-merchant-pppext-sonet-sdh-00.txt>

Shahrukh Merchant Cimaron Communications smerchant@cimaron.com +1 978 623-0009 Ext. 3020

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Purpose

• Document existing practice on previous technology (STS-3c, STS-12c)
• Document what appears to be consensus and/or current practice on

current technology (STS-48c)

• Propose extension for future technology (STS-192c)

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Philosophy

Preserve scope of PPP over SONET

• Do describe how to carry PPP over SONET
• Don’t describe how to map IP into PPP
• Don’t describe how to map SONET payloads into SONET frame

(The latter two are properly the domain of other standards and specifications) For extensions for future technology

• Practicality of implementation
• Retain familiarity of proven concepts where possible and reasonable

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STS-1, STS-3c, STS-12c

• HDLC per RFC 1662
• Revised ANSI T1.105.02 or Revised G.707 for SONET mapping

(C2=0x16, x43+1 payload scrambling)

STS-48c

• Same as above except FCS-32 is default (FCS-16 not a specified option)

Payload Extract SONET Frame x43+1 descrambler [Bypass opt] HDLC Frame Delineation Reverse tranparency processing FCS-16 Check [FCS-32 opt] Addr/Control Removal [Bypass opt] PPP Packet C2=0x16

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STS-192c

• 32-bit-oriented HDLC-32
• 32-bit alignment in SONET payload
• Eliminates options
• HDLC-32 payload scrambling prevents potential malicious bandwidth

expansion

STS-192c SONET x43+1 descrambler HDLC-32 Frame delin (32-bit-wise) Pad Removal 0-3 bytes 32→8 adapt PPP Packet Frame Payload extract (32-bit-align) Reverse tranparency proc (32-bit) x29+1 (?) descrambler FCS-32 Check C2=0x17

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HDLC-32 Motivation

• Byte-wise HDLC processing is extremely complicated at high rates (where

internal data bus widths are much wider) → 32-bit-wide processing

• Retain familiarity and proven approach of HDLC, modifying minimally as

needed to accommodate 32-bit-wide processing — Error in an HDLC frame rarely affects adjacent HDLC frames — Independent of packet format and length — Stream-based (no storage required beyond a few bytes for internal buffering)

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HDLC-32 Frame Format

Flag is one of: Flag0 or Flag1 or Flag2 or Flag3 Flag0 = E7 81 CA 34 Flag1 = E7 81 CA 35 Flag2 = E7 81 CA 36 Flag3 = E7 81 CA 37 Esc32 = EB 8D C6 38 Abort = Esc32 + Flag0

Flag Flag Flag Data Data . . . Data Data + pad FCS-32 Flag0,1,2,3 Flag

Flag0-3 or Esc32 replaced by

Indicates pad size

Esc32 + (Data ⊕ 0x20202020)

32 bit 32 bit

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Errata and Omissions in Submitted Document

• “No FCS” is not an option (for STS-1/3c/12c/48c)—must be FCS-16 or -32
• FCS-16 is not a specified option for STS-48c
• ACCM is not used (although an HDLC decoder would always decode it

properly anyway)

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Next Steps

• Incorporate comments, discussions and suggestions
• Fill in Appendix A, B, C (clarifying bit ordering of scrambling and CRC

calculations)

• Fill in Appendix D (PPP over DS3) and expand to include DS1-DS3 and

E1-E3