Reconfigurable and High Performance Computing Lab INAOE – Puebla, Mexico Embedded vision with FPGA vs CUDA processing. Directions and platform proposal WASC 2014 20 June 2014 Dr. Miguel Arias Estrada ariasmo@inaoep.mx
Content Introduction 1. Previous work on FPGA architectures 2. FPGA cameras 3. Platform proposal: FPGA vs CUDA 4. Long term project 5. Conclusions 6.
Reconfigurable and High Performance Computing Laboratory l Computer Science Department n 4 Researchers n 10+ M.Sc. Students n 5+ Ph.D. Students l Active since1998 l Research on: n Real time computer vision n Criptography and Cipher n Hardware Signal Processing
1. Introduction Smart camera approach High performance low level vision computing at camera 3D Vision, tracking / surveillance applications
2. Previous work on FPGA architectures Edge / Corner Detection Stereo disparity Target Tracking Motion correlation and Optical Flow 3D from Optical Flow SIFT / SURF / LISF feature detection
Approach l Off-the-shelf development boards l Focus on FPGA architecture. Application can be built in parallel l Goal: Reach video rate processing (i.e. 30 fps)
Edge and corner detection � Industrial applications � Basis for other image processing applications
Edge and corner detection architecture 0 COR 0 0 N COR N 0 COR 0 COR 1 1 N COR 1 N 1 1 COR 2 2 N COR N 2 COR 2 COR 2 3 N 3 COR R R N 3 3 COR M COR 3 A A M P U 4 M COR COR 4 M M 4 COR O X 4 N 1 T 2 N 4 COR 5 S 5 COR COR 5 5 N 5 N COR 6 COR 6 N 6 COR 6 N 6 • • • • • • N N-1 COR N Address Generator Decodificador
Demostration with RC200
Target tracking REGISDTRO VEN TANA VEN TANA D E PRO CESADO R (HEADER) P AT RÓN BÚSQUEDA DE CORRELACIÓN Target processor FPGA implementation
Multiple object tracking
Performance gain Algorithm acceleration 25 x to 50x compared to PC computer Drawback Modularity and reuse Lack of standards for vision cores
3. FPGA based cameras Overview of : Early concept Current approaches
Smart camera architecture Image and inter- mediate data buffer Smart camera High level processor (PC or robot CPU) Memory Imager L Host Comm FPGA Computer Imager R High BW channel (Ethernet or USB2.0) Reconfigurable processor One or - Soft processor (ctrl) two (stereo) - Parallel processor imagers - I/O and device interfaces
FPGA camera
Custom Spartan6 development board
FPGA ¡camera ¡– ¡2012/2013 ¡ USB 3.0 5 Megapixeles Spartan 6 device FPGA for sensor control and data packaging FPGA room for additional processing
FPGA ¡camera ¡prototype
4. Platform proposal Current work FPGA/Arm platform + Camera Tegra K1 platform + Camera
4.1 FPGA based Proposal l Use of a SoC (System on a Chip) l FPGA + ARM processor + Embedded Linux l Xilinx Zynq7000 + support electronics l Reconfiguration + I/O flexibility
FPGA platform
FPGA Platform :: MicroZed l Xilinx XC7Z010 l USB 2.0 l Gbit Ethernet l 1 Gbyte SRAM DDR3 l 128 Mb Flash l Micro SD card l 100 I/O l Embedded Linux
4.2 CUDA platform
CPU vs GPU ALU ALU Control ALU ALU GPU CPU Cache DRAM DRAM 25
CUDA programming �
FPGA vs Embedded CUDA FPGA CUDA • Low power • Easy to program • High performance • Speed up Advantages • Small size, possible • Floating point to migrate to VLSI • Complex to • Reformulate in implement parallel: core + • Long to learn memory use Inconvenient • Architecture • Power consumption complexity vs speedup
5. Long term project l Image + Feature extraction in Camera l Form descriptor extraction at the camera level (best for CUDA programing) l Host computer or Cloud for high level cognitive modeling / BigData techniques l Network of cameras can open new research possibilities
PARTIAL CORRESPONDENCE OF FORM � Object recognition using form • From a given object model, select a subset of • corresponding edge segments. Clasificación de objetos en imágenes usando características de forma
PARTIAL CORRESPONDENCE OF FORM CHALLENGE ¡ Part of the contour can be connected incorrectly with the background or other object, giving a wrong edge to be matched Clasificación de objetos en imágenes usando características de forma
OCTAR FORM DESCRIPTOR � • Open contour • Self-contained • Rotation and translation invariant
PARTIAL CORRESPONDENCE OF FORM FORM ¡DESCRIPTOR ¡
PARTIAL CORRESPONDENCE OF FORM OBJECT ¡LOCATION ¡ Each partial • correspondence vote for the center of the object Clasificación de objetos en imágenes usando características de forma
PARTIAL CORRESPONDENCE OF FORM OBJECT ¡LOCATION ¡ Fragments that can • be part of the object Clasificación de objetos en imágenes usando características de forma
6. Conclusions l FPGA based processing for low level feature extraction l Form descriptors and medium level processing is better with CUDA based platform l Potential to combine networks of cameras with embedded vision processing and Cloud computing
Laboratorio de Cómputo Reconfigurable y de Alto Desempeño Miguel Arias – Computer Sc. Dept. ariasmo@inaoep.mx
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