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Operating Systems Spring 2003 Ittai Abraham Zinovi Rabinovich The School of Computer Science and Engineering The Hebrew University of Jerusalem Operating Systems p.1 Course Information Lecturer: Gregory (Grisha) Chockler

SLIDE 1

Operating Systems

Spring 2003

Ittai Abraham Zinovi Rabinovich The School of Computer Science and Engineering The Hebrew University of Jerusalem

Operating Systems – p.1

SLIDE 2

Course Information

Lecturer: Gregory (Grisha) Chockler (grishac@cs.huji.ac.il) Teaching Assistants Ittai Abraham, ittaia@cs.huji.ac.il Zinovi Rabinovich, nomad@cs.huji.ac.il URL: http://www.cs.huji.ac.il/ ˜ os Newsgroups: Moderated: local.course.os.ta Non-moderated: local.course.os.st

Operating Systems – p.2

SLIDE 3

Administration and Rules

All regulations and requirements are clearly stated in the course homepage. In case of differences - the homepage version is compelling There are 6 exercises: 3 programming + 3 theoretical Your grade will be based on 5 best Programming exercises can be done in pairs (but not in larger groups) Exercises are 40% of the grade OS: Linux Language: C, C++, English

Operating Systems – p.3

SLIDE 4

Administration and Rules

Late submissions: 3 points one day 6 points for two days later submissions are not allowed All exercises have an automatic 3 point bonus Irurim: bonus is automatically lost no later then 2 weeks from the date the grades have been given

Operating Systems – p.4

SLIDE 5

Administration and Rules

Miluim: Up to 10 days no changes More then 10 days excuse one exercise (but not for the partner that remains) If there are two partners from different pairs where in every pair on e partner is in miluim, the pairs may merge The TA must be notifies in advance about miluim period (os@cs.huji.ac.il only)

Operating Systems – p.5

SLIDE 6

Administration and Rules

Submission: tar file containing the README, source files, make files see the detailed instructions on the exercise page tar cvf exN.tar <files> submit the tar file using browser submit theoretical exercise using the course mailbox keep your own version of the exercise

Operating Systems – p.6

SLIDE 7

Collaboration

We encourage you to collaborate on homework. However: You must write up solutions on your own You may not look at or copy other people solutions You may not provide solutions to be copied. Neither by allowing access nor by creating a commonly accessed copy of your solution If you do collaborate on homework, you must cite, in your written solution, all of your collaborators. If you use sources beyond the course materials in one

f your solutions, be sure to include a proper scholarly

citation of the source.

Operating Systems – p.7

SLIDE 8

Bibliography

Maurice J. Bach, The design of the UNIX Operating System Richard W. Stevens, Advanced Programming in the UNIX

Environment

Samuel J. Leffer et. al., The Design and Implementation of the

4.3 BSD OS

Raj Jain, The art of computer system performance analysis

Operating Systems – p.8

SLIDE 9

I never saw a wild thing sorry for itself. A bird will fall frozen dead from a bough without ever having felt sorry for itself.

Operating Systems – p.9

SLIDE 10

Computer System Structures

Interrupts DMA Memory Hierarchy

Operating Systems – p.10

SLIDE 11

General Structure

CPU

disk controller printer controller

D1 D2

printer memory controller

memory system bus

Operating Systems – p.11

SLIDE 12

Interrupts

Interrupts are signals about events

Operating Systems – p.12

SLIDE 13

Interrupts

Interrupts are signals about events Triggered by hardware

Operating Systems – p.12

SLIDE 14

Interrupts

Interrupts are signals about events Triggered by hardware Division by zero

Operating Systems – p.12

SLIDE 15

Interrupts

Interrupts are signals about events Triggered by hardware Division by zero Keyboard input

Operating Systems – p.12

SLIDE 16

Interrupts

Interrupts are signals about events Triggered by hardware Division by zero Keyboard input Disc completed writing a requested block

Operating Systems – p.12

SLIDE 17

Interrupts

Interrupts are signals about events Triggered by hardware Division by zero Keyboard input Disc completed writing a requested block Each interrupt has a ’service routine’ responsible for dealing with the event

Operating Systems – p.12

SLIDE 18

Interrupt Handling I

Interrupts are handled using the following sequence CPU is interrupted - stop whatever it does and..

Operating Systems – p.13

SLIDE 19

Interrupt Handling I

Interrupts are handled using the following sequence CPU is interrupted - stop whatever it does and.. ...find where service routine is and...

Operating Systems – p.13

SLIDE 20

Interrupt Handling I

Interrupts are handled using the following sequence CPU is interrupted - stop whatever it does and.. ...find where service routine is and... ...execute service routine..

Operating Systems – p.13

SLIDE 21

Interrupt Handling I

Interrupts are handled using the following sequence CPU is interrupted - stop whatever it does and.. ...find where service routine is and... ...execute service routine.. .. go back to whatever you did

Operating Systems – p.13

SLIDE 22

Interrupt Handling II

How do we find where service routine is?

Operating Systems – p.14

SLIDE 23

Interrupt Handling II

How do we find where service routine is? There is a predefined number of interrupts - use table of pointers (to functions)

Operating Systems – p.14

SLIDE 24

Interrupt Handling II

How do we find where service routine is? There is a predefined number of interrupts - use table of pointers (to functions) But where is the table?

Operating Systems – p.14

SLIDE 25

Interrupt Handling II

How do we find where service routine is? There is a predefined number of interrupts - use table of pointers (to functions) But where is the table?

Interrupt array starts at a predefined address in low

memory (100 first locations)

Operating Systems – p.14

SLIDE 26

Interrupt Handling II

How do we find where service routine is? There is a predefined number of interrupts - use table of pointers (to functions) But where is the table?

Interrupt array starts at a predefined address in low

memory (100 first locations) How do we know which table entry corresponds to a given interrupt?

Operating Systems – p.14

SLIDE 27

Interrupt Handling II

How do we find where service routine is? There is a predefined number of interrupts - use table of pointers (to functions) But where is the table?

Interrupt array starts at a predefined address in low

memory (100 first locations) How do we know which table entry corresponds to a given interrupt? Interrupt array is indexed by a unique device number

Operating Systems – p.14

SLIDE 28

Interrupt Handling II

How do we find where service routine is? There is a predefined number of interrupts - use table of pointers (to functions) But where is the table?

Interrupt array starts at a predefined address in low

memory (100 first locations) How do we know which table entry corresponds to a given interrupt? Interrupt array is indexed by a unique device number The number is assigned when the device is registered (asks for interrupt assignment)

Operating Systems – p.14

SLIDE 29

Interrupt Handling III

How do we know where to go back to?

Operating Systems – p.15

SLIDE 30

Interrupt Handling III

How do we know where to go back to? Keep ’a bookmark’ of where you stooped - use regular nested stack

Operating Systems – p.15

SLIDE 31

Interrupt Handling III

How do we know where to go back to? Keep ’a bookmark’ of where you stooped - use regular nested stack We stop whatever we do to handle an interrupt. Even a service routine?

Operating Systems – p.15

SLIDE 32

Interrupt Handling III

How do we know where to go back to? Keep ’a bookmark’ of where you stooped - use regular nested stack We stop whatever we do to handle an interrupt. Even a service routine? Not always. Usually interrupts are disabled during a service routine execution.

Operating Systems – p.15

SLIDE 33

Interrupt Handling III

How do we know where to go back to? Keep ’a bookmark’ of where you stooped - use regular nested stack We stop whatever we do to handle an interrupt. Even a service routine? Not always. Usually interrupts are disabled during a service routine execution. Computer architecture exist that allow nested interrupt handling.

Operating Systems – p.15

SLIDE 34

Interrupt Handling III

How do we know where to go back to? Keep ’a bookmark’ of where you stooped - use regular nested stack We stop whatever we do to handle an interrupt. Even a service routine? Not always. Usually interrupts are disabled during a service routine execution. Computer architecture exist that allow nested interrupt handling. These architectures usually use a priority scheme - interrupts with higher priority can break a servicing routine of a lower priority interrupts.

Operating Systems – p.15

SLIDE 35

DMA - Direct Memory Access

DMA is just another controller

Operating Systems – p.16

SLIDE 36

DMA - Direct Memory Access

DMA is just another controller DMA receives address of a buffer in memory and address of a block on disk from CPU

Operating Systems – p.16

SLIDE 37

DMA - Direct Memory Access

DMA is just another controller DMA receives address of a buffer in memory and address of a block on disk from CPU DMA runs the interaction between the disk and memory to transfer the required information

Operating Systems – p.16

SLIDE 38

DMA - Direct Memory Access

DMA is just another controller DMA receives address of a buffer in memory and address of a block on disk from CPU DMA runs the interaction between the disk and memory to transfer the required information It then interrupts CPU to inform about the operation completion

Operating Systems – p.16

SLIDE 39

DMA - Direct Memory Access

DMA is just another controller DMA receives address of a buffer in memory and address of a block on disk from CPU DMA runs the interaction between the disk and memory to transfer the required information It then interrupts CPU to inform about the operation completion Why is it good?

Operating Systems – p.16

SLIDE 40

DMA - Direct Memory Access

DMA is just another controller DMA receives address of a buffer in memory and address of a block on disk from CPU DMA runs the interaction between the disk and memory to transfer the required information It then interrupts CPU to inform about the operation completion Why is it good? It frees CPU to do other things while I/O operation is in progress

Operating Systems – p.16

SLIDE 41

Memory Hierarchy

registers cashe main memory magnetic disk

ptical disk

magnetic tapes

Speed/Cost Size

Operating Systems – p.17