[PPT] - N a n o s c a l e S S i l i c o n B a s e d N PowerPoint Presentation

SLIDE 1

C h u n g w

K

i m, P h . D . cw_kim@samsung.com

N a n

s

c a l e N a n

s

c a l e S i l i c

n

B a s e d S i l i c

n

B a s e d N

n

v

l

a t i l e M e mo r y N

n

v

l

a t i l e M e mo r y

SLIDE 2

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Acknowledgements Acknowledgements

S e

u

l N a n t i

n

a l U n i v e r s i t y ( S N U ) P r

f

. P a r k , B y u n g

G
K

K

r

e a I n s t i t u t e f

r

A d v a n c e d S t u d y ( K I A S ) P r

f

. K i m, D a e M a n n K w a n g j u I n s t i t u t e

f

S c i e n c e a n d T e c h n

l
g

y ( K J I S T ) P r

f

. H w a n g , H y u n s a n g S u n g k y u n k w a n U n i v e r s i t y P r

f

. C h u n g I l s u b C

r

n e l l U n i v e r s i t y , U S A P r

f

. S a n d i p T i w a r i I n s t i t u t e

f

S e mi c

n

d u c t

r

P h y s i c s , R u s s i a P r

f

. V l r a d mi r G r i t s e n k

Collaboration

Funding

T e r a

l

e v e l N a n

d

e v i c e s 2 1

s t

C e n t u r y F r

n

t i e r R & D P r

g

r a m, M i n i s t r y

f

S c i e n c e a n d T e c h n

l
g

y S E C a n d S A I T

SLIDE 3

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Introduction Current research status

– Nano fabrication Process

Nanoscale patterning
SiN thin film
Si Nanoparticle

– Nano devices

Nanoscale SONOS memory
Vertical channel memory

Future Work

Outline Outline

SLIDE 4

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

New application, unification

– Diversfied from PC into digital application – Increasing capacity of voice, motion picture information ➙ Need higher density of memory – Increasing demand for unified memory

Uncertainty of DRAM & Flash Memory scalability Memory Market: $35 billion (2001), $72 billion (2010), 8.3% increase/year

Environment of Memory Environment of Memory

Settop box PDA HHP Internet PC Digital TV Game Player

SLIDE 5

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Flash Memory Roadmap Flash Memory Roadmap

( S

u

r c e : I T R S 2 1 )

nm

1995 2000 2005 2010 2015

100 30

Feature Size Year

Unit Cell Production

Uncertain Stage Research Stage

64-512M

Develop. Stage

130 180 70 50 150 10

128-512M 128M-1G 256M-1G 256M-2G 512M-4G 512M-4G 2G-16G 4G-64G

Scale limit ?

SLIDE 6

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

참고자료 : ITRS 2001

Year of Production Flash tech. Node, F[nm] NAND highest W/E Voltage[V] NOR highest W/E Voltage[V] NOR tunnel dielectric thickness[nm] NAND tunnel dielectric thickness[nm] NOR interpoly dielectric thickness[nm] NAND interpoly dielectric thickness[nm] 2001 2002 2003 2004 2005 2006 2007 150 130 115 100 90 80 70 8-10 8-10 7-9 7-9 7-9 19-21 18-20 17-19 18-20 18-20 18-20 17-19 8-10 8-10 9.5-10.5 9.5-10 9-10 9-10 8.5-9.5 8.5-9.5 8.5-9.5 8.5-9.5 8.5-9 8-9 8-9 8-9 7.5-8 7.5-8 13-15 12-14 11-13 11-13 10-12 9-11 9-11 14-16 13-15 12-14 12-14 12-14 11-13 10-12

Solutions Exist Solutions are Known Solutions are NOT Known

Flash Technology Requirements Flash Technology Requirements

( S

u

r c e : I T R S 2 1 )

SLIDE 7

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

What’s the limits of flash scaling ? Floating poly Stack Active (STI)

Problems of conventional technologies

SLIDE 8

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Overcome Overcome

Control Gate Blocking oxide

e

Tunnel Oxide

e e e e Discrete traps n+ n+ p-well

SONOS Memory

Control Gate Blocking oxide

n+ n+ p-well

Tunnel Oxide

Floating gate e e e

기존 Flash memory

e e e e e e

☞ Discrete traps (SiN traps or Nanocrystal)

Discrete traps Discrete traps

* SONOS (Silicon-Oxide-Nitride-Oxide-Silicon)

SLIDE 9

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

< Advantages >

Compatibility of SONOS with CMOS with the use of thin nitride
Lower programming voltage
Smaller dimension capability than FG EEPROM
Longer retention & low defect induced tunneling leakage

(Nitride instead of poly Si )

Higher programming speed (depends on ONO thickness)

T r a p s i t e s

p

S

i

G a t e

30nm

S D

30 nm

US Patent # 6313503 (2001.11.6)

Motivation for SONOS Motivation for SONOS

SLIDE 10

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

4~10 F2 20~120 ns 1 µs ~ 1 ms >10년 > 1E5 6 F2 10~100 ns 10~100 ns > 10년 > 10E13 8~9 F2 10~100 ns 10~15 ns > 10년 > 1E13

FRAM

8~25 F2 30~200 ns 30 ns > 10년 > 10E12 Cell size Read time Write time Retention Endurance

Thin Oxide film Faster P/E time Power consumption Etching process Uniform thin films Cost

Issues

MRAM PRAM SONOS

Low High High Low Current/Power Low Low High High Cost CMOS Special Special Special Process

Etching process Cost Retention, Fatigue

Comparison of Memory Technologies Comparison of Memory Technologies

SLIDE 11

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

2 1

C h a n n e l L e n g t h

130 nm 130 nm 70 nm 70 nm

30 nm 30 nm

2 2 2 3

Source Drain Gate 70nm

SONOS Memory Development SONOS Memory Development

SLIDE 12

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Nano Nano Lithography Lithography

2 n m 6 n m

21 nm 32 nm

Sidewall Patterning

Positive Resist : PMMA Negative Resist : Calixarene

SLIDE 13

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Si Nanoparticle Si Nanoparticle Fabrication by Aerosol Laser Ablation Fabrication by Aerosol Laser Ablation

10 20 30 40 50 60 70 80 1x10

4

2x10

4

3x10

4

4x10

4

5x10

4

6x10

4

Concentration (/cm

3)

Nanoparticle Size (nm)

D <10nm
ρ ~ 1×1011 /cm2

5nm 5nm

SLIDE 14

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

30 30nm SONOS Memory by SWP nm SONOS Memory by SWP

10

7

10

6

10

5

10

4

10

3

10

2

10

1

10 10

1

10

2

10

3

2.0
1.5
1.0
0.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Vg=10 Vg=-10/Vd=4 Vg=-10/Vd=3 Vg=-10/Vd=2 Vg=-10/Vd=1

ONO=23/120/45 Å

Vg=-10

Threshold Voltage [V] Write/Erase Time [Sec]

Key Features of SONOS Cell Memory Node Size: 30 x 30 nm2 Write/ Erase Voltage: <10V Write/Erase Time: 1 msec Endurance: >106 cycles Retention = 1year @T=85℃

SLIDE 15

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Key Characteristics of SONOS Memory Key Characteristics of SONOS Memory

1.0
0.5

0.0 0.5 1.0

1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 1E-7 1E-6

Vth=-0.05V

W/L=30nm/30nm ONO=23/120/45 A VDS=1V VDS=0.1V

S.S = 89mV/dec DIBL = 105mV Drain Current [A] Vgs [V]

0.0 0.2 0.4 0.6 0.8 1.0

0.00E+000 4.00E-008 8.00E-008 1.20E-007 1.60E-007 2.00E-007 2.40E-007 2.80E-007 3.20E-007 3.60E-007

ONO=23/120/45 Å 1.0V 0.8V 0.6V 0.4V 0.2V VGS=0V

Drain Current [A] Vds [V]

10

2 10
1 10

0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8

2
1

1 2 3 1.4 [V]

Time [sec] Vth [V]

A t 85C @ Program state @ Erase state

10 10

1

10

2

10

3

10

4

10

5

10

6

1.0
0.5

0.0 0.5 1.0 1.5

Program m ed @ 10V/1m s Erased @

10V/10m

s

Vth (V) C ycles (num ber)

SLIDE 16

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY Drain Source Gate

SONOS Memory by E-beam Lithography SONOS Memory by E-beam Lithography

SONOS Cell by E-beam Lithography

W/L : 33nm / 46nm

SLIDE 17

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

20Å / 70Å / 90Å

SiO2= 20Å Si3N4= 70Å SiO2=90Å

TEM of the ONO (2 nm/7 nm/9 nm) stack
Auger profile showing the stoichiometric of ONO layer.

ONO layer TEM & AES Analysis ONO layer TEM & AES Analysis

3000 6000 9000 12000 15000 18000 20 40 60 80 100

Relative ACP(% )

Si N O

Sputter Time [sec.]

SLIDE 18

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

0.4
0.2

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8

Threshold Voltage[V] Write Time[sec] |9V| |10V| |11V| |12V| |13V|

1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1

0.4
0.2

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

Threshold Voltage[V] Erase Time[sec] |9V| |10V| |11V| |12V| |13V|

∆Vth ~ 2.4V Trapped Charge density = 4.1 ~ 5.9 x 1012 cm –2

No. of e- = 61 ~ 88 for 33nm x 46nm node size

∆Vth ~ 2.4V Trapped Charge density = 4.1 ~ 5.9 x 1012 cm –2

No. of e- = 61 ~ 88 for 33nm x 46nm node size

Program & Erase Program & Erase Characterisics Characterisics

SLIDE 19

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Memory window is nearly similar for SONOS devices with different memory node areas

Memory Window Comparison Memory Window Comparison

2
1

1 2 3 4 5 6 7 8 9 10 10

15

1x10

14

1x10

13

1x10

12

1x10

11

1x10

10

1x10

9

1x10

8

1x10

7

1x10

6

1x10

5

Wg/Lg=90nm / 100nm Id [A] Vg [V]

Wg/Lg=90nm/100nm

2
1

1 2 3 4 5 6 7 8 9 10 10

15

1x10

14

1x10

13

1x10

12

1x10

11

1x10

10

1x10

9

1x10

8

1x10

7

1x10

6

1x10

5

Wg/Lg=75nm / 100nm Id [A] Vg [V]

Wg/Lg=75nm/100nm

2
1

1 2 3 4 5 6 7 8 9 10 10

15

1x10

14

1x10

13

1x10

12

1x10

11

1x10

10

1x10

9

1x10

8

1x10

7

1x10

6

1x10

5

Wg/Lg=62nm / 60nm Id [A] Vg [V]

Wg/Lg=62nm/60nm

2
1

1 2 3 4 5 6 7 8 9 10 10

15

1x10

14

1x10

13

1x10

12

1x10

11

1x10

10

1x10

9

1x10

8

1x10

7

1x10

6

1x10

5

Wg/Lg=33nm / 46nm Id [A] Vg [V]

Wg/Lg=33nm/46nm

SLIDE 20

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Retention time is good with 75nm

width and 100 nm length at 85℃.

Retention Time Retention Time Endurance Endurance

10

1

10 10

1

10

2

10

3

10

4

10

5

10

6

10

7

10

8

10

9

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Wg/Lg=75nm / 100nm Temp=85C

Threshold Voltage [V] Retention Time[sec]

Write 10V, 10msec Erase -10V, 1msec 10

1

10

2

10

3

10

4

10

5

10

6

0.6 0.8 1.0 1.2 1.4 1.6 1.8

Temp=85C Wg/Lg=33nm / 46nm

Threshold Voltage [V] Write/Erase Cycle

Write 12V/10msec Erase -10V/1msec

It remains unchanged up to 105

cycles, indicating superior endurance characteristics at 85℃.

SLIDE 21

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Single electron charging effect at 30 nm dimensions.

Memory Effect at 30 nm dimensions Memory Effect at 30 nm dimensions

Wg = 35.4 nm Lg = 39 nm

1

1 2 3 4 0.0 2.0x10

10

4.0x10

10

6.0x10

10

8.0x10

10

1.0x10

9

1.2x10

9

1.4x10

9

W

g/L g=35n

m / 39n m

B efore w rite A fter w rite(10m s,|10V |)

ID [A ] V G [V ]

SLIDE 22

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

Vertical Channel SONOS

N+ N+ Poly Silcon BOX

Schematic of VC SONOS

1E-4 1E-3 0.01 0.1

0.8
0.4

0.0 0.4 0.8 1.2 1.6 2.0

0.001

Vg 6/7/8V Erased Cell Programmed Cell Vg -6/-7/-8V Vth (V) Write/Erase Time(sec)

Id=1nA, Vd=0.5V

∆Vth=1.6V @ 8/-8V &10ms

SLIDE 23

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY

TEM images

Gate CVD oxide Vertical channel O/N/O Contact Vertical channel bulk Drain Source Gate

source drain gate

SLIDE 24

C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003

ADVANCED INSTITUTE OF TECHNOLOGY