N a n o s c a l e S S i l i c o n B a s e d N - PowerPoint PPT Presentation

N a n o s c a l e S S i l i c o n B a s e d N a n o s c a l e i l i c o n B a s e d N o n v o l a t i l e M e mo r y N o n v o l a t i l e M e mo r y C h u n g w o o K i m, P h . D . cw_kim@samsung.com

Acknowledgements Acknowledgements Collaboration C o r n e l l U n i v e r s i t y , U S A S e o u l N a n t i o n a l U n i v e r s i t y ( S N U ) P r o f . S a n d i p T i w a r i P r o f . P a r k , B y u n g - G o o K I n s t i t u t e o f S e mi c o n d u c t o r P h y s i c s , R u s s i a K o r e a I n s t i t u t e f o r A d v a n c e d S t u d y P r o f . V l r a d mi r G r i t s e n k o ( K I A S ) P r o f . K i m, D a e M a n n Funding K w a n g j u I n s t i t u t e o f S c i e n c e a n d T e r a - l e v e l N a n o d e v i c e s T e c h n o l o g y ( K J I S T ) 2 1 s t C e n t u r y F r o n t i e r R & D P r o g r a m, M i n i s t r y o f S c i e n c e a n d T e c h n o l o g y P r o f . H w a n g , H y u n s a n g S E C a n d S A I T S u n g k y u n k w a n U n i v e r s i t y P r o f . C h u n g I l s u b ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Outline Outline � Introduction � Current research status – Nano fabrication Process • Nanoscale patterning • SiN thin film • Si Nanoparticle – Nano devices • Nanoscale SONOS memory • Vertical channel memory � Future Work ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Environment of Memory Environment of Memory � New application, unification – Diversfied from PC into digital application – Increasing capacity of voice, motion picture information ➙ Need higher density of memory – Increasing demand for unified memory � Uncertainty of DRAM & Flash Memory scalability � Memory Market: $35 billion (2001), $72 billion (2010), 8.3% increase/year Game Settop Player box Digital TV PDA HHP Internet PC ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Flash Memory Roadmap Flash Memory Roadmap ( S o u r c e : I T R S 2 0 0 1 ) nm 180 Unit Cell Develop. Stage 64-512M Production 150 Feature Size 128-512M 130 128M-1G 256M-1G Research Stage 100 256M-2G Scale limit ? 512M-4G 512M-4G 70 2G-16G 50 Uncertain Stage 4G-64G 30 10 1995 2000 2005 2010 2015 Year ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Flash Technology Requirements Flash Technology Requirements ( S o u r c e : I T R S 2 0 0 1 ) Year of Production 2001 2002 2003 2004 2005 2006 2007 Flash tech. Node, F[nm] 150 130 115 100 90 80 70 NOR highest W/E Voltage[V] 8-10 8-10 8-10 8-10 7-9 7-9 7-9 NAND highest W/E Voltage[V] 19-21 18-20 18-20 18-20 18-20 17-19 17-19 NOR tunnel dielectric thickness[nm] 9.5-10.5 9.5-10 9-10 9-10 8.5-9.5 8.5-9.5 8.5-9.5 NAND tunnel dielectric thickness[nm] 8.5-9.5 8.5-9 8-9 8-9 8-9 7.5-8 7.5-8 NOR interpoly dielectric thickness[nm] 13-15 12-14 11-13 11-13 10-12 9-11 9-11 NAND interpoly dielectric thickness[nm] 14-16 13-15 12-14 12-14 12-14 11-13 10-12 참고자료 : ITRS 2001 Solutions Exist Solutions are Known Solutions are NOT Known ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Problems of conventional technologies � What’s the limits of flash scaling ? Stack Floating poly Active (STI) ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Discrete traps Discrete traps Floating gate Discrete traps Control Gate Blocking oxide Control Gate Overcome Overcome e e e e Blocking oxide e e e e e e e e e e Tunnel Oxide Tunnel Oxide n+ n+ n+ n+ p-well p-well 기존 Flash memory SONOS Memory ☞ Discrete traps (SiN traps or Nanocrystal) * SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Motivation for SONOS Motivation for SONOS G a t e T r a p s i t e s 30nm 30 nm S D p - S i US Patent # 6313503 (2001.11.6) < Advantages > • Compatibility of SONOS with CMOS with the use of thin nitride • Lower programming voltage • Smaller dimension capability than FG EEPROM • Longer retention & low defect induced tunneling leakage (Nitride instead of poly Si ) • Higher programming speed (depends on ONO thickness) ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Comparison of Memory Technologies Comparison of Memory Technologies FRAM MRAM PRAM SONOS Cell size 8~25 F 2 8~9 F 2 6 F 2 4~10 F 2 Read time 30~200 ns 10~100 ns 10~100 ns 20~120 ns Write time 1 µ s ~ 1 ms 30 ns 10~15 ns 10~100 ns > 10 년 > 10 년 > 10 년 >10 년 Retention Endurance > 10E12 > 1E13 > 10E13 > 1E5 Current/Power Low High High Low Cost High High Low Low Process Special Special Special CMOS Etching process Etching process Power Thin Oxide film Uniform thin films Issues Cost consumption Faster P/E time Cost Retention, Fatigue ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

SONOS Memory Development SONOS Memory Development 130 nm 130 nm C h a n n e l L e n g t h 70 nm 70 nm Source Gate 30 nm 30 nm Drain 70nm 2 0 0 1 2 0 0 2 2 0 0 3 ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Nano Lithography Lithography Nano 21 nm 2 0 n m 6 0 n m Positive Resist : PMMA 32 nm Sidewall Patterning Negative Resist : Calixarene ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Si Nanoparticle Fabrication by Aerosol Laser Ablation Fabrication by Aerosol Laser Ablation Si Nanoparticle 4 6x10 3 ) Concentration (/cm 4 5x10 4 4x10 • D <10nm 4 3x10 • ρ ~ 1 × 10 11 /cm 2 4 2x10 4 1x10 0 0 10 20 30 40 50 60 70 80 Nanoparticle Size (nm) 5nm 5nm ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

30nm SONOS Memory by SWP nm SONOS Memory by SWP 30 3.0 ONO=23/120/45 Å 2.5 Threshold Voltage [V] 2.0 Vg=10 1.5 1.0 0.5 Vg=-10 0.0 Vg=-10/Vd=1 -0.5 Vg=-10/Vd=2 -1.0 Vg=-10/Vd=3 -1.5 Vg=-10/Vd=4 -2.0 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 10 10 10 10 10 10 10 10 10 10 10 Write/Erase Time [Sec] Key Features of SONOS Cell � Memory Node Size: 30 x 30 nm2 � Write/ Erase Voltage: <10V � Write/Erase Time: 1 msec � Endurance: >10 6 cycles � Retention = 1year @T=85 ℃ ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Key Characteristics of SONOS Memory Key Characteristics of SONOS Memory 3 3.60E-007 1.0V ONO=23/120/45 Å 3.20E-007 Drain Current [A] 0.8V 2 0.6V 2.80E-007 1.4 [V] 2.40E-007 1 A t 85C Vth [V] 0.4V 2.00E-007 @ Program state @ Erase state 1.60E-007 0 0.2V 1.20E-007 -1 8.00E-008 V GS =0V 4.00E-008 -2 -2 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 0.00E+000 8 10 0.0 0.2 0.4 0.6 0.8 1.0 Time [sec] Vds [V] 1.5 1E-6 W/L=30nm/30nm V DS =1V 1E-7 ONO=23/120/45 A 1.0 Drain Current [A] 1E-8 V DS =0.1V 1E-9 0.5 Vth (V) Program m ed @ 10V/1m s 1E-10 Erased @ -10V/10m s DIBL = 105mV 0.0 1E-11 S.S = 89mV/dec V th =-0.05V 1E-12 -0.5 1E-13 1E-14 -1.0 -1.0 -0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 10 10 10 10 10 10 10 Vgs [V] C ycles (num ber) ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

SONOS Memory by E-beam Lithography SONOS Memory by E-beam Lithography Drain Gate Source SONOS Cell by E-beam Lithography W/L : 33nm / 46nm ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

ONO layer TEM & AES Analysis ONO layer TEM & AES Analysis 100 80 Si N SiO 2 =90Å Relative ACP(% ) O Si 3 N 4 = 70Å 60 SiO 2 = 20Å 40 20 20Å / 70Å / 90Å 0 0 3000 6000 9000 12000 15000 18000 Sputter Time [sec.] • TEM of the ONO (2 nm/7 nm/9 nm) stack • Auger profile showing the stoichiometric of ONO layer. ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY

Program & Erase Characterisics Characterisics Program & Erase 3.0 |9V| 2.8 2.8 |9V| |10V| 2.6 2.6 |10V| |11V| 2.4 2.4 |11V| |12V| 2.2 2.2 |12V| |13V| 2.0 2.0 Threshold Voltage[V] |13V| Threshold Voltage[V] 1.8 1.8 1.6 1.6 1.4 1.4 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 0.0 -0.2 -0.2 -0.4 -0.4 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 1E-7 1E-6 1E-5 1E-4 1E-3 0.01 0.1 1 Write Time[sec] Erase Time[sec] � ∆ Vth ~ 2.4V � ∆ Vth ~ 2.4V � Trapped Charge density = 4.1 ~ 5.9 x 10 12 cm –2 � Trapped Charge density = 4.1 ~ 5.9 x 10 12 cm –2 � No. of e - = 61 ~ 88 for 33nm x 46nm node size � No. of e - = 61 ~ 88 for 33nm x 46nm node size ADVANCED INSTITUTE C.W. Kim, KOREA-US Nano Forum, Oct. 14, 2003 OF TECHNOLOGY