MPSoC 2006 TM tech DaVi Vinci nci TM chno nolo logy gy fo for - - PDF document

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MPSoC 2006 TM tech DaVi Vinci nci TM chno nolo logy gy fo for - - PDF document

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MPSoC 2006 TM tech DaVi Vinci nci TM chno nolo logy gy fo for di digi gital tal vi vide deo ap o appl plicati cations ns Deepu Talla, Ph.D. System Architect 1 Overview DaVinci TM technology overview DM644x SoC architecture

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SLIDE 1

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1

DaVi Vinci nciTM

TM tech

chno nolo logy gy fo for di digi gital tal vi vide deo ap

  • appl

plicati cations ns

Deepu Talla, Ph.D. System Architect

MPSoC 2006

2

Overview

  • DaVinciTM technology overview
  • DM644x SoC architecture
  • Software platform overview
  • Video performance
  • Power management
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SLIDE 2

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3

Digital media SoC platform

Flexibility for Innovation Integration-Level

ASIC ASSP FPGA DSP CPU

4

Processors: Digital video system-on-chips

DVEVM

Digital Video Evaluation Module

Tools: Validated software and hardware development

– TMS320DM6443 – Video decode – TMS320DM6446 – Video encode/decode

DM644x

– Platform-optimized, multimedia codecs – Platform support package – Linux support package

Software: Open, optimized and production tested

– Industry-recognized APIs – Multimedia frameworks

Complete offering to enable digital video innovation

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SLIDE 3

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5

Video chip evolution

10/100 Ethernet MAC EMIF 8-bit McASP 66 MHz PCI Enhanced DMA Controller L1D Cache 16 KBytes L1P Cache 16 KBytes C64x

TM

DSP Core L2 Cache/Memory 256 KBytes Video port-0 Video port-1 Video port-2 32-bit HPI TMS320DM642 2 McBSPs Enhanced DMA Controller L1D Cache 16 KBytes L1P Cache 16 KBytes C64x

TM

DSP Core L2 Cache/Memory 1M Bytes TMS320C6414

McBSP 0 McBSP 1 McBSP 2 HPI32 EMIF 16 EMIF 64 Video Processing Subsystem Video Processing Subsystem Peripherals Back End ARM Subsystem DSP Subsystem

Video-Imaging Coprocessor (VICP) Front End CCD Controller Video Interface Resizer Histogram/3A Preview On-Screen Display (OSD) 10b DAC 10b DAC 10b DAC 10b DAC EDMA ATA/ Compact Flash Async EMIF/ NAND/ SmartMedia MMC/ SD Watchdog Timer PWM PWM PWM General- Purpose Timer DDR2 Controller (16b/32b) USB 2.0 PHY VLYNQ EMAC With MDIO Connectivity Program/Data Storage SPI UART UART UART I2C Audio Serial Port Serial Interfaces System ARM926EJ-S 300 MHz CPU C64x+TM DSP 600 MHz Core Switched Central Resource (SCR) Video Enc (VENC)

DaVinci™

2001 2003 2005

Video-capable DSP Digital Media Processor Digital Media SOC

6

Quality Multi-Format Video Encode/Decode Support

  • 600 MHz C64x+ DSP
  • Video Accelerators
  • High Bandwidth DDR2 Memory

Interface

  • Integrated Video Output

System Integration & Flexibility

  • 300 MHz ARM Host Processor
  • Programmable for Changing

Standards

System Connectivity

  • Ethernet MAC for Streaming

Video

  • USB 2.0 for Consumer

Peripherals

Video Storage

  • ATA HDD interface
  • True IDE Compact Flash

Interface

Dedicated Video Processing Sub-system

  • Front end – Resizer, Image

processing engine, 16-bit digital input

TMS320DM644x block diagram

ARM9

DSP

600-MHz Core

L2 SRAM 64kB Prog L1 SRAM 32kB Prog 80kB Data

ARM9

300-MHz CPU

16kB I$, 8kB D$ 16kB SRAM, ROM

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SLIDE 4

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Video Optimized C64x+™ DSP

DM644x™ Feature

Video Optimized DSP

Video

Acceleration

32kB L1P Cache/

SRAM

80kB L1D SRAM

  • Up to 32kB

Cache

64kB L2

Cache/SRAM

600 MHz

Programmability C64x+ CPU

SPLOOP Buffer 16-Bit Instruction Coding

Benefit

Video

H.264 MP D1 Decoding VC-1/WMV9 D1 Decoding MPEG-2 MP@ML D1 Decoding MPEG-4 ASP D1 Decoding H.264 BP D1 Encoding Simultaneous H.264 BP CIF Enc/Dec

Audio (Concurrent with Video)

MPEG-4 AAC LC and HE MP3 MPEG-1 Layer 1&2

Security

128-Bit AES Decryption Microsoft DRM Support Multi-Format Video Capability Future Proof – Easily Upgradeable 100% Code Compatible from C64x™ Greater than 20% Code Size

Reduction

DM644x VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connec- tivity C64x+™ DSP Switched Central Resource C64x+ Megamodule C64x+ CPU

Data Path 1 Data Path 2 M2 xx xx D2 S2 L2 A Register File B Register File Instruction Decode 16/32-bit Instruction Dispatch Instruction Fetch Interrupt & Exception Controller S1 L1 M1 xx xx D1 Unified Memory Controller (UMC) Data Memory Controller (DMC) 32 64 Memory Protection Bandwidth Mgmt. External Memory Controller (EMC) DMA Slave I/F IDMA 128 256 256 SPLOOP Buffer Program Memory Controller (PMC) Memory Protection Bandwidth Mgmt. Bandwidth Mgmt. Memory Protection 256 128 256 Master Port (CPU/ cache req.) 128 Power Control 256 256

80 KB L1D Cache/SRAM 32 KB L1P Cache/SRAM 64K Cache/SRAM

128 256

Video Acceleration

8

ARM host

DM644x

VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connectivity C64x+ DSP Switched Central Resource

DM644x™ Feature

  • ARM9 Host

Processor

  • 300 MHz
  • Memory
  • 8kB Data Cache
  • 16kB Instruction

Cache

  • 16kB RAM

Benefit

  • Standard OS Environment
  • Flexible Network Protocol

Options

  • Simplifies User Interface
  • System Control Flexibility
  • Efficient Application

Execution

ARM Subsystem ARM926EJ

  • S

I-cache 16KB RAM 16KB D-cache 8KB Boot ROM ARM Interrupt Cntl.

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SLIDE 5

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Video processing sub system

DM644x Feature

  • Integrated Video Output
  • RGB888 @ 75 MHz
  • BTU656 : 8 or 16 bit @ 75 MHz
  • Support for Standard LCD I/F
  • 4 10-bit 54MHz DACs
  • Composite
  • S-Video
  • Component: RGB, YPbPr
  • NTSC/PAL: 480/576 Interlaced
  • NTSC/PAL: 480/576 Progressive
  • Integrated Video Input
  • CCD/CMOS Interface
  • 16 bit at 75 MHz
  • BTU601/656 Interface
  • 8 or 16 bit at 75 MHz
  • Color Space Conversion
  • Preview en
  • Bayer RGB to YCbCr 4:2:2 color

space conversion

Benefit

  • Optimized Video System

Cost

  • Standard Encoder

Connectivity

  • Integrated Display Driver
  • Multi-Format Support
  • Optimized Video System

Cost

  • Analog Codec Connectivity
  • Digital Video Interface
  • Glueless Camera Interface
  • Video Format Flexibility
  • Off loads the DSP
  • Programmable noise filter

Composite & S-Video, or Composite & Component (YPbPr),

  • r SCART (Composite + RGB)

DM644x VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connec- tivity C64x+™ DSP Switched Central Resource

VPSS Resizer OSD Video Out Histogram /H3A Preview en Video In VPSS Resizer OSD Video Out Histogram /H3A Preview en Video In

10

Video processing sub system (continued)

DM644x Feature

On Screen Display (OSD) Video Window

  • RGB888
  • YCbCr 4:2:2

One OSD Bitmap Window

  • RGB656
  • One Attribute Window
  • 8 levels of blending

Resizer 4x to 1/4x Resizing

  • N/256 Zoom step

Linear and Bi-Cubic Resize Algorithm Histogram/H3A Statistical Engine for Calculating Exposure, White Balance, and Focus Histogram data collection Statistics collected in RGB Color Space ARM and/or DSP can use these statistics to control camera functions

Benefit

  • Picture in Picture

Capability

  • Easy to Use Attribute

Window

  • On Screen Application

Control

  • Automatic Video

Rescale

  • Offload CPU Processing
  • Automatic Focus

Control

  • Automatic White

Balance Correction

  • Automatic Exposure

Compensation

Composite & S-Video, or Composite & Component (YPbPr),

  • r SCART (Composite + RGB)

DM644x VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connec- tivity C64x+™ DSP Switched Central Resource

VPSS Resizer OSD Video Out Histogram /H3A Previewer Video In VPSS Resizer OSD Video Out Histogram /H3A Previewer Video In

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SLIDE 6

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Memory and storage interfaces

DM644x™ Feature

DDR2-333 32-Bit Interface Up to 256MB 166 MHz Clock Hard Disk Interface ATA/ATAPI-5 HDD Interface True IDE Compact Flash Shared with EMIF EMIF 4 Chip Selects NAND Flash Connection

  • 2 x 8/16-bit NAND

Devices

  • SM/xD

Asynchronous Memory Shared with ATA MMC/SD

Benefit

  • Quality Video

Processing

  • Advanced Codec

Capability

  • Local Video Storage
  • Easy Boot

Configuration

  • Expansion Capability
  • MultiMedia Card

Interface

DM644x VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connect- ivity C64x+™ DSP Switched Central Resource

DDR2-32b AEMIF-16b ATA/CF MMC/SD OR

12

Advanced connectivity

VLYNQ™ USB 2.0 EMAC

DM644x™ Feature

Ethernet MAC

  • 10/100 Mb/s
  • MII to Switch or PHY
  • MDIO Interface

USB 2.0

  • LNK + PHY
  • High Speed (480Mps)
  • Host or client

VLYNQ™

  • 75 MHz Serial Connection
  • 4 Serial Receive Pins
  • 4 Serial Transmit Pins

Benefit

Real-Time Streaming Video Integration Optimizes Cost Standard Expansion

Interface

High-speed Video Uploads FPGA Interface 802.11 WLAN Interface

DM644x VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connec- tivity C64x+™ DSP Switched Central Resource

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SLIDE 7

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Serial interfaces

Benefit

  • Low Cost Codec

Connectivity

  • Audio Format Flexibility
  • Bluetooth Interoperability
  • Remote Control Capability
  • Peripheral Configuration
  • Peripheral Configuration
  • PLL Synchronization
  • PTZ/Focus Camera Control
  • Optional User Peripherals

DM644x Feature

  • Audio Serial Port
  • AC97 Support
  • I2S Audio Connection
  • UART (3)
  • One with Flow Control
  • I2C
  • SPI (2)
  • PWM (3)
  • GPIO

DM644x VPSS Memory I/F Serial I/F ARM Subsystem Advanced Connec- tivity C64x+™ DSP Switched Central Resource UART (x3) GPIO PWM (x3) Audio SP I2C SPI (x2)

14

Software platform overview

ARM9 RISC

Linux

Device Drivers

C64x+ DSP

DSP/BIOS LINK DSP/ BIOS

Socket Nodes

Video ImagingSpeech Audio

ARM/DSP Communication

Codec Abstraction APIs

Developer Software

Applications, Framework and GUI

Developer Software

Applications, Framework and GUI

Model 1 User

VLYNQ Peripheral Cache EDMA Timer I2C UART EMAC ATA INTC MMC NAND SPI USB 2.0 Audio SP Video Out Video In VLYNQ Peripheral Cache EDMA Timer I2C UART EMAC ATA INTC MMC NAND SPI USB 2.0 Audio SP Video Out Video In

Standard OS Drivers Peripheral APIs

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SLIDE 8

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Video performance in an end system

D1+ D1+ H.264 (Main Profile) Decode n/a D1+ H.264 (Baseline) Encode D1+ D1+ H.264 (Baseline) Decode n/a D1+ VC1/WMV 9 Encode 720p+ 720p+ VC1/WMV 9 Decode n/a 720p+ MPEG-2 SP Encode 720p+ 720p+ MPEG-4 SP Decode n/a D1+ MPEG-2 MP ML Encode 720+ 1080i+ (60 fields/30 frames) MPEG-2 MP ML Decode Standalone Codecs

TMS320DM6443 TMS320DM6446

Benchmarks: DM644x Video Capabilities

16

Power management

  • Intended to be used for battery powered devices and not just wall plugged applications
  • Voltage scaling

– From 1.2V to 0.95V core VDD → up to 37% reduction in active power and 50% reduction in leakage

  • Process compensation

– Blow fuses for voltage compensation; increase voltage for weak process and decrease voltage for strong process → 100-200 mV reduction in core voltage

  • Multiple Vt transistors

– Trade-off area, speed, and power using high Vt, standard Vt, and Long L transistors → up to 50% reduction in leakage power

  • Pre-silicon power simulations

– Improve RTL and microarchitecture based on power simulations → 50% reduction in active power in key blocks

  • Multiple power domains

– DSP and VICP on separate power domain from rest of the core VDD → 50% reduction in leakage power

  • Mode aware IO

– Turn off DDR2 SSTL1.8V IO receivers when not doing reads → 40mW power savings when no reads to DDR2

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SLIDE 9

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17

Ques uesti tion

  • ns

MPSoC 2006