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Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache - - PowerPoint PPT Presentation

Oct 04, 2023 376 likes •686 views

Michele TORTELLI Dario ROSSI Emilio LEONARDI Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache Networks 23rd ICNRG MeeIng (Interim) 14/15-01-2016 michele.tortelli@telecom-paristech.fr M OTIVATION Simula2on is the primary tool

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SLIDE 1

Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache Networks

Michele TORTELLI Dario ROSSI Emilio LEONARDI 23rd ICNRG MeeIng (Interim) – 14/15-01-2016 michele.tortelli@telecom-paristech.fr

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SLIDE 2

MOTIVATION

Simula2on is the primary tool for performance evaluaIon of cache networks. Some phenomena only appear @ scale…

[1] K. PenIkousis et al., InformaIon-centric networking: EvaluaIon methodology, Internet Dra* - (Oct. 2015)

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4-level Binary Tree Constant C/M = 0.1%, Zipf’s α = 1, IRM

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

Web catalog size esImate [1] (opImisIc)

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SLIDE 3

People have limited CPU & Memory budgets

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

ccnSim v0.3 ccnSim v0.4-alpha CPU = 1.2 h Memory = 2.15 GB

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SLIDE 4

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

ccnSim v0.3 ccnSim v0.4-alpha

People have limited CPU & Memory budgets

CPU = 1.2 h Memory = 2.15 GB CPU = 1.1 h Memory = 673 MB

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SLIDE 5

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

CPU = 1.2 h Memory = 2.15 GB ccnSim v0.3 ccnSim v0.4-alpha CPU = 1.1 h Memory = 673 MB CPU = ~1/2 day Memory = 6.8 GB

People have limited CPU & Memory budgets

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SLIDE 6

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

ccnSim v0.3 ccnSim v0.4-alpha CPU = ~1/2 day Memory = 6.8 GB

People have limited CPU & Memory budgets

CPU = ~5 days Memory = 68 GB

One order of magnitude more becomes resource expensive

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SLIDE 7

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

ccnSim v0.3 ccnSim v0.4-alpha

People have limited CPU & Memory budgets

CPU = ~5 days Memory = 68 GB CPU = ~50 days Memory = 680 GB CPU = ~1/2 day Memory = 6.8 GB

Two orders of magnitude more become really cumbersome

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SLIDE 8

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

ccnSim v0.3 ccnSim v0.4-alpha

People have limited CPU & Memory budgets

CPU = ~50 days Memory = 680 GB CPU = >1 year Memory = ~7 TB CPU = ~5 days Memory = 68 GB CPU = ~1/2 day Memory = 6.8 GB

Three orders of magnitude more become unfeasible

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SLIDE 9

5 10 15 20 25 30 35 1e2 1e5 1e3 1e6 1e4 1e7 1e5 1e8 1e6 1e9 1e7 1e10 1e8 1e11 1e9 1e12 5 10 15 20 25 |Cache| (C) |Catalog| (M) Phit[%] C/75-th percentile Phit C / 75-th percentile

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SIMULATION LIMITATIONS

ccnSim v0.3 ccnSim v0.4-alpha

People have limited CPU & Memory budgets

CPU = ~50 days Memory = 680 GB CPU = >1 year Memory = ~7 TB CPU = ~5 days Memory = 68 GB CPU = ~1/2 day Memory = 6.8 GB

Require careful instrumentaIon Event-driven Simula2on à Massive compuIng power at large scale Inefficient (wasIng Ime and memory with expected events)

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SLIDE 10

IDEA

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GAIN

Downscaling M, C, and R with factor Δ RejecIon Inversion Sampling Error correcIon with feedback loop Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on Time to Live (TTL) caches

CPU & Memory CPU & Memory Memory Stability & Accuracy

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SLIDE 11

IDEA

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GAIN

Downscaling M, C, and R with factor Δ RejecIon Inversion Sampling Error correcIon with feedback loop Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on Time to Live (TTL) caches

CPU & Memory CPU & Memory Memory Stability & Accuracy

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SLIDE 12

IDEA

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GAIN

Downscaling M, C, and R with factor Δ RejecIon Inversion Sampling Error correcIon with feedback loop Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on Time to Live (TTL) caches

CPU & Memory CPU & Memory Memory Stability & Accuracy

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SLIDE 13

IDEA

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GAIN

Downscaling M, C, and R with factor Δ RejecIon Inversion Sampling Error correcIon with feedback loop Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on Time to Live (TTL) caches

CPU & Memory CPU & Memory Memory Stability & Accuracy

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SLIDE 14

IDEA

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GAIN

Downscaling M, C, and R with factor Δ RejecIon Inversion Sampling Error correcIon with feedback loop Downscaled MonteCarlo TTL-based (MC-TTL) Simula2on Time to Live (TTL) caches

CPU & Memory CPU & Memory Memory Stability & Accuracy

  • Ex. with Δ=1e5

~100x CPU & Memory gain

~2% Accuracy

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SLIDE 15

Model

UNDER THE HOOD

SCENARIO DESCRIPTION RESULTS

MC-TTL SimulaIon

TC TC guess

Topology RouIng and Forwarding Cache Replacement Policy Cache Decision Policy Content popularity Catalog cardinality (M) Cache size (C) Number of requests (R) Downscaling factor (Δ) Yora (Y)

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SLIDE 16

Model

UNDER THE HOOD

SCENARIO DESCRIPTION RESULTS

MC-TTL SimulaIon

TC TC guess

Topology RouIng and Forwarding Cache Replacement Policy Cache Decision Policy Content popularity Catalog cardinality (M) Cache size (C) Number of requests (R) Downscaling factor (Δ) Yora (Y)

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DOWNSCALING & SAMPLING

Δ

M C R M’ = M / Δ CT = C / Δ R’ = R / Δ Downscaled catalog Target cache Dowscaled # events

Backup slides for technical details

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SLIDE 17

RESULTS I – VERY LARGE SCENARIO

Cache Decision Policy Phit CPU | Gain Mem [MB]| Gain

LCE

SimulaIon 33.2 11.4 h

160x

6371

168x

MC-TTL 31.4 256 s 38

FIX0.1

SimulaIon 35.4 7.3 h

90x

6404

168x

MC-TTL 34.0 291 s 38

2-LRU

SimulaIon 37.0 10.8 h

97x

8894

234x

MC-TTL 36.1 402 s 38

4-level Binary Tree

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|Cache|

  • C = 1e6

|Catalog|

  • M = 1e9

# Requests

  • R = 1e9

Downscaling Factor

  • Δ = 1e5
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SLIDE 18

RESULTS II – WEB SCALE SCENARIO

  • 1 cache entry

≈ 165 Bytes

  • 1 catalog entry = 4 Bytes
  • Fix cost

≈ 19.83 MB

Memory Model FiUng (Simulator)

CDN-like: N~60 - M=1e11 - C=1e7

M

Technique MC-TTL SimulaIon (Est) Mem[MB] CPU Cycles Mem[MB] CPU 4-level Binary Tree

Parameters

M=R=1e10 - C=1e6 - Δ=1e5 45 0.4 h 1 70000 4.7 days CDN-like (N=67) M=R=1e11 - C=1e7 - Δ=1e6 31 12.5 h 3 520000 ~50 days

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Mem = (1.65 10-4) N C + 4 10-6 M + 19.83 [MB]

(ccnSim v0.4-alpha with rejecIon inversion sampling)

2.0E+10 4.0E+10 6.0E+10 8.0E+10 1.0E+11 1.2E+11 1.4E+11 1.6E+11 1.8E+11 20 40 60 80 100 120 140 160 180 200 N 0.0*100 2.0*105 4.0*105 6.0*105 8.0*105 1.0*106 1.2*106 64 GB 512 GB 1 TB

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SLIDE 19

CONCLUSIONS

Extreme scalability, general methodology

Implementable in every simulator (ndnSIM, Icarus, …)

Available in ccnSim v0.4-alpha

(hrp://perso.telecom-paristech.fr/~drossi/ccnSim)

Technical Report (slightly old)

  • M. Tortelli, D. Rossi and E. Leonardi,

Model-Gra*: Accurate, Scalable and Flexible Analysis of Cache Networks

  • Tech. Rep. [CCN-TR15], Telecom ParisTech, 2015.

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SLIDE 20

THANK YOU

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QUESTIONS

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SLIDE 21

BACKUP SLIDES

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SLIDE 22

CHE’S APPROXIMATION

TC(m) = TC

Cache evic)on )me for content m (i.e., interval of Ime a*er which ‘m’ is evicted) Assumed to be CONSTANT, independent from the content

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SLIDE 23

UNDER THE HOOD

INITIALIZATION MC-TTL SIMULATION CYCLE

CT CM(z) TC(z+1) DOWNSCALING & SAMPLING CONTROLLER: TC CORRECTION STABILITY CHECK MC-TTL SIMULATION CONSISTENCY CHECK

Model

SCENARIO DESCRIPTION RESULTS

MC-TTL SimulaIon

TC TC guess

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SLIDE 24

DOWNSCALING & SAMPLING

DOWNSCALING & SAMPLING

Δ

M C R M’ = M / Δ CT = C / Δ R’ = R / Δ Downscaled catalog Target cache Dowscaled # events

. . .

1 2 3 M’ BINS 1 2 3 M’

. . .

META CONTENTS

Rejec2on Inversion Sampling (VERY SCALABLE!)

Extract Zipf’s distributed random numbers between [1, Δ] No Memory and Ο(1) runIme complexity

Meta content n-th bin Requested with probability Δ contents of the n-th bin

NOT SCALABLE! M’ Ο(Δ) init cost M’ Ο(Δ) space cost Ο(logΔ) sampling Ime

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SLIDE 25

STABILITY CHECK

Pivotal role to simulate the R’(1) requests at steady state Dynamic transient period (rouIng, meta-caching, topology,…) Adap2ve Stability Monitor

ED-Sim: end = R / (Λ*Cl), with MC-TTL: end’ = R’ / (Λ’*Cl), with Since end = end’ à R’ = R / Δ (1)

Coefficient of VariaIon (CV) of the mean hit probability ( CV = std(phit) / E(phit) ) Batch mean of W samples (new sample iif acIve cache and state change) Check stability (i.e., CV < 5 10-3) for the first N’ = Y N nodes, where Y ∈ ]0,1].

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SLIDE 26

TC CORRECTION & CONSISTENCY CHECK

Hp: each TTL cache will store, on average, CT = C/∆ contents at steady state if its evic+on +me corresponds to the characteris+c +me TC of its equivalent LRU non-scaled cache. Controlled Variable = Measured Cache Size CM

CMi(k+1) = online avg of the cache size of the i-th node @ k-th measurement Ime Bi(k+1) = actual # contents stored inside the TTL cache Samples are taken every miss event with probability p=0.1

Consistency Check (a*er R’ events)

Same N’ nodes (coherent with stability check) End MC-TTL simulaIon Correct Tc and start new MC-TTL cycle CM distance from CT connected to input TC distance from real TC (the higher TC the bigger CM)

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SLIDE 27

TC SENSITIVITY - I

Tc Values [s] Level LCE FIX0.1 LCD 2-LRU (Name/Main) 0 (Root) 11 115 13 14 / 654 1 22 218 1090 27 / 1040 2 43 400 1250 51 / 1420 3 (Leaves) 75 570 815 75 / 1255 P_hit @ Stab. 22.8 25.9 28.5 29.2 P_hit @ End. 22.8 26.3 28.1 29.4

  • Stab. Time

8.4 10.3 14.4 23.7 End Time 482.7 390 386 456.3

4-level Binary Tree

|Cache|

  • C = 1e3

|Catalog|

  • M = 1e6

# Requests

  • R = 1e7

Downscaling Factor

  • Δ = 1e2
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SLIDE 28

TC SENSITIVITY - II

50 100 150 200 TC/(100*r) TC TC*(100*r) 0.5 1 1.5 2 2.5 164x 1.9% 12x Computational Gain Accuracy Loss[%] Input Tc values

Computational Gain Accuracy Loss

LCE

Simula2on: Phit = 30.6% - CPU = 4089 s

  • Mem = 673 MB

Model: Phit = 29.8% - CPU = 740 s

  • Mem = 24240 MB

MC-TTL:

  • Mem ≈ 38 MB (18x)

4-level Binary Tree

|Cache|

  • C = 1e5

|Catalog|

  • M = 1e8

# Requests

  • R = 1e8

Downscaling Factor

  • Δ = 1e4
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SLIDE 29

YOTTA SENSITIVITY

  • Sim. Type

Yora P_hit @ Stab. P_hit @ End

  • Stab. Time [s]

End Time [s]

ED-Sim

1 33.8 33.9 99.7 458.0 0.95 33.7 33.9 42.4 432.5 0.9 33.7 33.9 35.0 421.9 0.75 33.6 33.9 29.3 408.13 0.5 32.8 33.9 15.4 401.33

NDN Testbed

|Cache|

  • C = 1e3

|Catalog|

  • M = 1e6

# Requests

  • R = 1e7

Downscaling Factor

  • Δ = 1e3