Mitigating Wordline Crosstalk using Adaptive Trees of Counters - - PowerPoint PPT Presentation

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Mitigating Wordline Crosstalk using Adaptive Trees of Counters - - PowerPoint PPT Presentation

May 30, 2023 191 likes •527 views

Mitigating Wordline Crosstalk using Adaptive Trees of Counters Mohammad Seyedzadeh , Alex Jones, Rami Melhem University of Pi8sburgh Wordline Crosstalk in DRAM DRAM Scaling High Memory Capacity Voltage Fluctua<ons DRAM Cells

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SLIDE 1

Mitigating Wordline Crosstalk using Adaptive Trees of Counters

Mohammad Seyedzadeh, Alex Jones, Rami Melhem

University of Pi8sburgh

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SLIDE 2

2

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Deep-scaled DRAM Cells DRAM Cells

Wordline Crosstalk in DRAM

DRAM Scaling

✔ High Memory Capacity ✖ Voltage Fluctua<ons

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SLIDE 3

2

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Deep-scaled DRAM Cells DRAM Cells

Wordline Crosstalk in DRAM

Row of Cells

DRAM Bank

Row of Cells

Wordline

Vic@m Row Aggressor Row Vic@m Row

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SLIDE 4

2

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Deep-scaled DRAM Cells DRAM Cells

  • The malicious exploit of this crosstalk by repeatedly accessing a row to induce this effect is known as

row hammering.

Wordline Crosstalk in DRAM

Row of Cells

DRAM Bank

Row of Cells

Wordline

Vic@m Row Aggressor Row Vic@m Row

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SLIDE 5
  • Wordline Crosstalk in DRAM
  • Probabilistic and Deterministic Solutions
  • CAT: Counter based Adaptive Tree
  • Evaluation
  • Conclusion

Outline

3

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

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SLIDE 6

4

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Deep-scaled DRAM Cells

Determinis<c Approach Probabilis<c Approach

Wordline Crosstalk in DRAM: Related Work

Static Counter Assignment (SCA) Probabilistic Row Activation (PRA)

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SLIDE 7

Probabilistic Row Activation (PRA)

5

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Probabilis<c Approach

Deep-scaled DRAM Cells

RNG(p)

  • Using a Random Number Generator to refresh the vic@m rows with the probability of ‘p’.
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SLIDE 8

1.E-28 1.E-24 1.E-20 1.E-16 1.E-12 1.E-08 1.E-04 1.E+00

32k 24k 16k 8k PRA Unsurvivability for 5 Years Refresh Threshold (T)

p=0.001 p=0.002 p=0.003 p=0.004 p=0.005 p=0.006 Chipkill

Probabilistic Row Activation (PRA)

6

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Refresh threshold: # of aggressor row accesses before read disturbance errors occur in vic@m rows. LFSR-based RNG Pseudo Random Number Generator (PRNG) PRA Failure Probability for 5 years

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SLIDE 9

1.E-28 1.E-24 1.E-20 1.E-16 1.E-12 1.E-08 1.E-04 1.E+00

32k 24k 16k 8k PRA Unsurvivability for 5 Years Refresh Threshold (T)

p=0.001 p=0.002 p=0.003 p=0.004 p=0.005 p=0.006 Chipkill

Probabilistic Row Activation (PRA)

6

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Refresh threshold: # of aggressor row accesses before read disturbance errors occur in vic@m rows. LFSR-based RNG PRA Failure Probability for 5 years

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SLIDE 10

1.E-28 1.E-24 1.E-20 1.E-16 1.E-12 1.E-08 1.E-04 1.E+00

32k 24k 16k 8k PRA Unsurvivability for 5 Years Refresh Threshold (T)

p=0.001 p=0.002 p=0.003 p=0.004 p=0.005 p=0.006 Chipkill

Probabilistic Row Activation (PRA)

6

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Refresh threshold: # of aggressor row accesses before read disturbance errors occur in vic@m rows. LFSR-based RNG PRA Failure Probability for 5 years

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SLIDE 11

Static Counter Assignment (SCA)

7

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Power to maintaining Counters P r e c i s e R e f r e s h P

  • w

e r P

  • w

e r t

  • m

a i n t a i n i n g C

  • u

n t e r s Conservative Refresh Power Deep-scaled DRAM Cells

C0 Cm

. . .

CN-1

. . . . . . . . .

Deep-scaled DRAM Cells

C0 Cn

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SLIDE 12

Static Counter Assignment (SCA)

8

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

  • Non-uniform row access pa8erns in DRAM banks because of data locality

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536

Energy (nJ) # of Counters

Counters (Sta:c+Dynamic) Refresh Total (refresh+counter energy)

Unu<lized Counters

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536

Energy (nJ) # of Counters

Counters (Sta:c+Dynamic) Refresh Total (refresh+counter energy)

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536

Energy (nJ) # of Counters

Counters (Sta:c+Dynamic) Refresh Total (refresh+counter energy)

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SLIDE 13

How to Efficiently Leverage Counters in the Crosstalk Mitigation?

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

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SLIDE 14

9

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Our Solution: Counter-based Adap@ve Tree (CAT)

Expired Counter DRAM BANK (N rows) Ac@ve Counter Row Address

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

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SLIDE 15

10

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Our Solution: Counter-based Adap@ve Tree (CAT)

Expired Counter Ac@ve Counter DRAM BANK (N rows) Row Address

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

Row Address

×104 1 2 3 4 5 6

Access Frequency

×104 2 4 6 8 10

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SLIDE 16

CAT: Counter based Adaptive Tree

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

² PRCAT: Periodically Reset CAT

Ø Burst Refresh Mechanism Ø Reset CAT at the end of each refresh Interval

² DRCAT: Dynamically Reconfigured CAT

Ø Distributed Refresh Mechanism Ø Reconfigure CAT during consecutive refresh intervals

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SLIDE 17

PRCAT: Periodically Reset CAT

12

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

C0 Burst Refresh 64ms 64ms

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SLIDE 18

PRCAT: Periodically Reset CAT

12

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Burst Refresh 64ms 64ms I0 C0 C1

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SLIDE 19

PRCAT: Periodically Reset CAT

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

I0 C0 I3 I2 C1 I4 C3 C6 I5 C4 C2 C5 Burst Refresh 64ms 64ms I1

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SLIDE 20

PRCAT: Periodically Reset CAT

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

I0 C0 I1 I3 I2 C1 I4 C3 I5 C4 C2 C5 I6 C7 C6 Burst Refresh 64ms 64ms

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SLIDE 21

PRCAT: Periodically Reset CAT

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

I0 C0 I1 I3 I2 C1 I4 C3 I5 C4 C2 C5 I6 C7 C6 Burst Refresh 64ms 64ms

Reset CAT

C0

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SLIDE 22

PRCAT: Periodically Reset CAT

12

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Burst Refresh 64ms 64ms

Reset CAT

C0

Build CAT from the Root

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SLIDE 23

DRCAT: Dynamically Reconfigured CAT

12

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

I0 C0 I1 I3 I2 C1 I4 C3 I5 C4 C2 C5 I6 C7 C6

Distributed Refresh

64ms 64ms

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SLIDE 24

DRCAT: Dynamically Reconfigured CAT

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

I0 C0 I1 I3 I2 C1 I4 C3 I6 C7 C6 I5 C4 C2 C5 C6 C2 C5

Distributed Refresh

64ms 64ms

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SLIDE 25

13

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

64ms 64ms

DRCAT: Dynamically Reconfigured CAT

Distributed Refresh

I0 C0 I1 I3 I2 C1 I4 C3 I6 C7 I5 C4 C5 C2 I5 C6

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SLIDE 26

C7

I3 C3

I2

I1 I6

I5

C1

C0 C4

I4

C2

I0

C5 C6

(b) (c) (d) (a)

I0 I1 C0 1 C0 I1 I2 I3 1 1 C1 I2 C1 I4 1 C2 1 I3 C3 I6 1 C3 1 I4 C5 C4 C4 I5 C6 C2 C5 I6 I5 C7 1 C6 1

L-ptr R-ptr L-leaf R-leaf C7

1

W C I M-1 M

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

I0 C0 I1 I3 I2 C1 I4 C3 I6 C7 I5 C4

DRCAT: Dynamically Reconfigured CAT

C5 C2 I5 C6

  • During each row access, the tree structure is traversed sequen@ally by chasing the pointers

to find the counter assigned to a specific row address.

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SLIDE 27

14

DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

Synopsys Design Compiler PARSEC, SPEC, Commercial and Biobench Power Overhead Performance Overhead Kernel Malicious A8ack USIMM Simulator: Two 3.2GHz cores, 2 channels(each 8GB DIMM), 1 rank/ channel 8 banks/rank, 64K rows/bank

Experimental Settings

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SLIDE 28

Power Overhead

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

0% 5% 10% 15% 20% 25% 30%

com1 com2 com3 com4 com5 swapt fluid str black ferret face freq MTC MTF libq leslie mum <gr Mean COMM PARSEC SPEC BIO

Probabilis<c Row Ac<va<on Sta<c Counter Assignment PRCAT DRCAT

  • Power overhead for DRCAT in dual-core systems is 4.5%, which is an improvement over the 12% and

13% incurred in PRA and SCA.

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SLIDE 29

Performance Overhead

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

  • DRCAT, PRCAT and PRA incur very low performance overhead (<0.5%).

0% 1% 2% 3% 4%

com1 com2 com3 com4 com5 swapt fluid str black ferret face freq MTC MTF libq leslie mum <gr Mean COMM PARSEC SPEC BIO

Probabilis<c Row Ac<va<on Sta<c Counter Assignment PRCAT DRCAT

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SLIDE 30

Sensitivity Analysis

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

0% 5% 10% 15% 20% 25% PRA_0.003 SCA_128 PRCAT_64 DRCAT_64 PRA_0.003 SCA_256 PRCAT_128 DRCAT_128 PRA_0.003 SCA_256 PRCAT_128 DRCAT_128 dual-core/2channels quad-core/2channels quad-core/4channels

Power Overhead

  • DRCAT reduces the power overhead in

quad-core systems to 7%, which is an improvement over the 21% and 18% incurred in SCA and PRA.

0% 5% 10% 15% PRA_0.001 SCA_128 PRCAT_32 DRCAT_32 PRA_0.002 SCA_128 PRCAT_64 DRCAT_64 PRA_0.003 SCA_128 PRCAT_64 DRCAT_64 PRA_0.005 SCA_256 PRCAT_12 DRCAT_12

Power Overhead

² Refresh Thresholds

² Mapping Policy & Number of Cores

  • Scaling down DRAM technology exacerbates

the crosstalk problem leading to a decrease in the refresh threshold.

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SLIDE 31

Performance Overhead under Malicious attacks

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

0% 1% 2% 3% 4% 5%

SCA_128 PRCBT_64 DRCBT_64 SCA_128 PRCBT_64 DRCBT_64 SCA_128 PRCBT_64 DRCBT_64 SCA_128 PRCBT_64 DRCBT_64 SCA_128 PRCBT_64 DRCBT_64 SCA_128 PRCBT_64 DRCBT_64 SCA_256 PRCBT_128 DRCBT_128 SCA_256 PRCBT_128 DRCBT_128 SCA_256 PRCBT_128 DRCBT_128 Heavy Medium Light Heavy Medium Light Heavy Medium Light T=32K T=16K T=8K

  • As expected, more intensive a8acks leads to higher ETO since it causes more refreshes.

<0.9%

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SLIDE 32

Conclusion

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree

  • Proposed a non-uniform counter assignment, Counter-Based Adap<ve Tree, to

more precisely determine the aggressor rows.

  • Introduced a scheme, DRCAT, for dynamically reconfiguring the CAT to track the

temporal changes in memory access pa8erns .

  • Demonstrated that a small number of counters can be implemented on chip to

mi@gate wordline crosstalk.

  • DRCAT avoids wordline crosstalk during normal execu@on and protects against

malicious aXacks.

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SLIDE 33

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DRCAT: Dynamically Reconfigured Counter based Adaptive Tree