Micro Processor & Controller Organization Organization Outline - - PowerPoint PPT Presentation

Organization Organization

Micro Processor & Controller

Outline Outline

Project Examples

– CPU 8, 16, 32 Bits – FPU

General Architecture of Computer

– CPU - MEM - I/O – Peripheral

Memory Hierarchy

– Main Memory – Auxiliary Memory

Considerations Considerations

Compromise between

– Performance (Memory, Speed) – Price – Size – Power consumption – Development Tools – Examples – Support

PIC16 PIC16 – – 8 bits DIP CPU : Sniff Probe 8 bits DIP CPU : Sniff Probe

PIC18 PIC18 – – 8 bits PLCC CPU : Pulse Generator 8 bits PLCC CPU : Pulse Generator

MSP430 MSP430 – – 16 bits CPU : Drug Detector 16 bits CPU : Drug Detector

C28335 C28335 Delfino Delfino – – 32 bits CPU + FPU 32 bits CPU + FPU

Concerto F28M35 Dual Core Concerto F28M35 Dual Core – – 32 bits M3+C28 32 bits M3+C28

TMS320DM6437 32/64 bits + DDR2 Memory TMS320DM6437 32/64 bits + DDR2 Memory

CPU CPU -

• Memory

Memory -

• I/O

I/O

CPU Memory I/O Pripheral

A.B. D.B. RD WR CS A.B. D.B. RD WR CS A.B. D.B. RD WR MEM IO ROM RAM FLASH I/O Map Keyboard Printer More ... Mouse

Controller = CPU + Memory + Peripheral Controller = CPU + Memory + Peripheral

A.B. D.B. RD WR CS ROM RAM FLASH EPROM A.B. D.B. RD WR CS Timer ADC UART PWM A.B. D.B. RD WR CS Register ALU FLAGS FPU

Memory Hierarchy Memory Hierarchy

CPU Cache L1 Cache L2 Main Mem

I/O Boundary

Hard Disk Magnetic Media Magnetic Tapes Optical Media Floppy Disk

Register Inside CPU Static RAM DRAM, ROM, EPROM, FLASH IDE, SCSI, SATA ZIP, JAZ, LS-120 DAT, Analog CD-ROM, CDR, CDRW, DVD Zevel

Internal

• r

External Bus I / O Mapping Devices

I/O Bus and Interface I/O Bus and Interface

CPU Interface Keyboard & Display Interface Printer Interface Hard Disk Interface USB

• r

LAN

Data Bus Addr Bus Control