Memory Management Disclaimer: some slides are adopted from book - - PowerPoint PPT Presentation

Memory Management

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Disclaimer: some slides are adopted from book authors’ slides with permission

Recap: Virtual Memory (VM)

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Process A Process B Process C Physical Memory

MMU

Recap: MMU

• Hardware that translates virtual addresses to

physical addresses

1) base register 2) base + limit registers (segmentation); 3) paging

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Recap: Page Table based Address Translation

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0x12345678

Ox12345 0x678

Page # Offset frame #: 0xabcde frame #

• ffset

0x678 0x12345

0xabcde678

Virtual address Physical address Page table

Recap: Translation Lookaside Buffer

• Cache frequent address translations

– So that CPU don’t need to access the page table all the time – Much faster

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Multi-level Paging

• Two-level paging

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Two Level Address Translation

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2nd level

• ffset

1st level 1st level Page table 2nd level Page table

Frame # Offset Base ptr

Virtual address Physical address

Example

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2nd level

• ffset

8 bits 8 bits

1st level

8 bits Virtual address format (24bits)

Vaddr: 0x0703FE 1st level idx: 07 2nd level idx: 03 Offset: FE Vaddr: 0x072370 1st level idx: __ 2nd level idx: __ Offset: __ Vaddr: 0x082370 1st level idx: __ 2nd level idx: __ Offset: __

Multi-level Paging

• Can save table space
• How, why?

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Quiz

• What is the minimum page table size of a

process that uses only 4MB memory space?

– assume a PTE size is 4B

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2nd level

• ffset

10 bits 12 bits

1st level

10 bits

• ffset

12 bits

1st level

20 bits

4 * 2^10 + 4* 2^10 = 8KB 4 * 2^20 = 4MB

Paging Summary

• Advantages

– Efficient use of memory space

• No external fragmentation
• Two main Issues

– Translation speed can be slow

• Solution: TLB

– Table size is big

• Solution: Multi-level page table

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Concepts to Learn

• Demand paging

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Virtual Memory (VM)

• Abstraction

– 4GB linear address space for each process

• Reality

– 1GB of actual physical memory shared with 20

• ther processes
• Does each process use the

(1) entire virtual memory (2) all the time?

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Demand Paging

• Idea: instead of keeping the entire memory

pages in memory all the time, keep only part

• f them on a on-demand basis

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Page Table Entry (PTE)

• PTE format (architecture specific)

– Valid bit (V): whether the page is in memory – Modify bit (M): whether the page is modified – Reference bit (R): whether the page is accessed – Protection bits(P): readable, writable, executable

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Page Frame No V M R P 20 bits 2 1 1 1

Partial Memory Mapping

• Not all pages are in memory (i.e., valid=1)

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Page Fault

• When a virtual address can not be translated

to a physical address, MMU generates a trap to the OS

• Page fault handling procedure

– Step 1: allocate a free page frame – Step 2: bring the stored page on disk (if necessary) – Step 3: update the PTE (mapping and valid bit) – Step 4: restart the instruction

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Page Fault Handling

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Demand Paging

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Starting Up a Process

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Unmapped pages

Code Data Heap Stack

Starting Up a Process

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Access next instruction

Code Data Heap Stack

Starting Up a Process

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Page fault

Code Data Heap Stack

Starting Up a Process

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OS 1) allocates free page frame 2) loads the missed page from the disk (exec file) 3) updates the page table entry

Code Data Heap Stack

Starting Up a Process

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Code Data Heap Stack

Over time, more pages are mapped as needed

Anonymous Page

• An executable file contains code (binary)

– So we can read from the executable file

• What about heap?

– No backing storage (unless it is swapped out later) – Simply map a new free page (anonymous page) into the address space

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Program Binary Sharing

• Multiple instances of the same program

– E.g., 10 bash shells

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Bash text Physical memory Bash #1 Bash #2