M Tool Set (for tool set release 2.0) R Todd M. Austin L - PowerPoint PPT Presentation

A User’s and Hacker’s Guide to the SimpleScalar Architectural Research M Tool Set (for tool set release 2.0) R Todd M. Austin L taustin@ichips.intel.com Intel MicroComputer Research Labs January, 1997 Todd M. Austin Page 1

Tutorial Overview • Computer Architecture Simulation Primer • SimpleScalar Tool Set q Overview q User’s Guide • SimpleScalar Instruction Set Architecture Out-of-Order Issue Simulator • q Model Microarchitecture q Implementation Details Hacking SimpleScalar • • Looking Ahead Todd M. Austin Page 2

A Computer Architecture Simulator Primer • What is an architectural simulator? q a tool that reproduces the behavior of a computing device System Outputs Device System Inputs Simulator System Metrics • Why use a simulator? q leverage faster, more flexible S/W development cycle q permits more design space exploration q facilitates validation before H/W becomes available q level of abstraction can be throttled to design task q possible to increase/improve system instrumentation Todd M. Austin Page 3

A Taxonomy of Simulation Tools Architectural Simulators Functional Performance Trace-Driven Exec-Driven Inst Schedulers Cycle Timers Interpreters Direct Execution • shaded tools are included in the SimpleScalar tool set Todd M. Austin Page 4

Functional vs. Performance Simulators Specification Arch uArch Development Spec Spec Simulation Arch uArch Sim Sim • functional simulators implement the architecture q the architecture is what programmer’s see • performance simulators implement the microarchitecture q model system internals (microarchitecture) q often concerned with time Todd M. Austin Page 5

Execution- vs. Trace-Driven Simulation • trace-based simulation: Simulator inst trace q simulator reads a “trace” of inst captured during a previous execution q easiest to implement, no functional component needed Simulator program execution-driven simulation: • q simulator “runs” the program, generating a trace on-the-fly q more difficult to implement, but has many advantages q direct-execution: instrumented program runs on host Todd M. Austin Page 6

Instruction Schedulers vs. Cycle Timers • constraint-based instruction schedulers q simulator schedules instructions into execution graph based on availability of microarchitecture resources q instructions are handled one-at-a-time and in order q simpler to modify, but usually less detailed • cycle-timer simulators q simulator tracks microarchitecture state for each cycle q many instructions may be “in flight” at any time q simulator state == state of the microarchitecture q perfect for detailed microarchitecture simulation, simulator faithfully tracks microarchitecture function Todd M. Austin Page 7

The Zen of Simulator Design Performance Performance: speeds design cycle Flexibility: maximizes design scope Pick Two Detail: minimizes risk Detail Flexibility • design goals will drive which aspects are optimized • The SimpleScalar Architectural Research Tool Set q optimizes performance and flexibility q in addition, provides portability and varied detail Todd M. Austin Page 8

Tutorial Overview • Computer Architecture Simulation Primer • SimpleScalar Tool Set q Overview q User’s Guide • SimpleScalar Instruction Set Architecture Out-of-Order Issue Simulator • q Model Microarchitecture q Implementation Details Hacking SimpleScalar • • Looking Ahead Todd M. Austin Page 9

The SimpleScalar Tool Set • computer architecture research test bed q compilers, assembler, linker, libraries, and simulators q targeted to the virtual SimpleScalar architecture q hosted on most any Unix-like machine • developed during my dissertation work at UW-Madison q third generation simulation system (Sohi → Franklin → Austin) q 2.5 years to develop this incarnation q first public release in July ‘96, made with Doug Burger q second public release in January ‘97 • freely available with source and docs from UW-Madison http://www.cs.wisc.edu/~mscalar/simplescalar.html Todd M. Austin Page 10

SimpleScalar Tool Set Overview Fortran code C code F2C GCC Assembly code GAS Simulators object files libf77.a libm.a GLD Executables libc.a Bin Utils • compiler chain is GNU tools ported to SimpleScalar • Fortran codes are compiled with AT&T’s f2c libraries are GLIBC ported to SimpleScalar • Todd M. Austin Page 11

Primary Advantages • extensible q source included for everything: compiler, libraries, simulators q widely encoded, user-extensible instruction format • portable q at the host, virtual target runs on most Unix-like boxes q at the target, simulators can support multiple ISA’s • detailed q execution driven simulators q supports wrong path execution, control and data speculation, etc... q many sample simulators included • performance (on P6-200) q Sim-Fast: 4+ MIPS q Sim-OutOrder: 200+ KIPS Todd M. Austin Page 12

Simulation Suite Overview Sim-Cache/ Sim-Fast Sim-Safe Sim-Profile Sim-Outorder Sim-Cheetah - 420 lines - 350 lines - 900 lines - < 1000 lines - 3900 lines - functional - functional - functional - functional - performance - 4+ MIPS w/ checks - lot of stats - cache stats - OoO issue - branch pred. - mis-spec. - ALUs - cache - TLB - 200+ KIPS Performance Detail Todd M. Austin Page 13

Simulator Structure User SimpleScalar Program Binary Programs Prog/Sim SimpleScalar ISA POSIX System Calls Interface Functional Machine Definition Proxy Syscall Handler Core BPred Stats Simulator Core Performance Resource Dlite! Core Cache Loader Regs Memory • modular components facilitate “rolling your own” • performance core is optional Todd M. Austin Page 14

Tutorial Overview • Computer Architecture Simulation Primer • SimpleScalar Tool Set q Overview q User’s Guide • SimpleScalar Instruction Set Architecture Out-of-Order Issue Simulator • q Model Microarchitecture q Implementation Details Hacking SimpleScalar • • Looking Ahead Todd M. Austin Page 15

Installation Notes • follow the installation directions in the tech report, and DON’T PANIC!!!! • avoid building GLIBC q it’s a non-trivial process q use the big- and little-endian, pre-compiled libraries in ss-bootstrap/ • if you have problems, send e-mail to the SimpleScalar mailing list: simplescalar@cs.wisc.edu • please e-mail install mods to: dburger@cs.wisc.edu x86 port has limited functionality, portability • q currently not supported q reportedly only works under little-endian Linux Todd M. Austin Page 16

Generating SimpleScalar Binaries • compiling a C program, e.g., ssbig-na-sstrix-gcc -g -O -o foo foo.c -lm • compiling a Fortran program, e.g., ssbig-na-sstrix-f77 -g -O -o foo foo.f -lm • compiling a SimpleScalar assembly program, e.g., ssbig-na-sstrix-gcc -g -O -o foo foo.s -lm running a program, e.g., • sim-safe [-sim opts] program [-program opts] • disassembling a program, e.g., ssbig-na-sstrix-objdump -x -d -l foo • building a library, use: ssbig-na-sstrix-{ar,ranlib} Todd M. Austin Page 17

Global Simulator Options • supported on all simulators: - print simulator help message -h - enable debug message -d - start up in DLite! debugger -i - terminate immediately (use with -dumpconfig ) -q - read configuration parameters from <file> -config <file> -dumpconfig <file> - save configuration parameters into <file> • configuration files: q to generate a configuration file: q specify non-default options on command line q and, include “ -dumpconfig <file> ” to generate configuration file q comments allowed in configuration files: q text after “ # ” ignored until end of line q reload configuration files using “ -config <file> ” q config files may reference other configuration files Todd M. Austin Page 18

DLite!, the Lite Debugger • a very lightweight symbolic debugger • supported by all simulators (except sim-fast) • designed for easily integration into SimpleScalar simulators q requires addition of only four function calls (see dlite.h ) • to use DLite!, start simulator with “ -i ” option (interactive) program symbols and expressions may be used in most contexts • q e.g., “ break main+8 ” • use the “ help ” command for complete documentation • main features: q break , dbreak , rbreak : set text, data, and range breakpoints q regs , iregs , fregs : display all, int, and FP register state q dump <addr> <count> : dump <count> bytes of memory at <addr> q dis <addr> <count> : disassemble <count> insts starting at <addr> q print <expr> , display <expr> : display expression or memory q mstate : display machine-specific state Todd M. Austin Page 19

DLite!, the Lite Debugger (cont.) • breakpoints: q code: q break <addr> q e.g., break main , break 0x400148 q data: q dbreak <addr> {r|w|x} q r == read, w == write, x == execute q e.g., dbreak stdin w , dbreak sys_count wr q code: q rbreak <range> q e.g., r break @main:+279 , r break 2000:3500 • DLite! expressions q operators: +, -, /, * q literals: 10, 0xff, 077 q symbols: main, vfprintf q registers: $r1, $f4, $pc, $fcc, $hi, $lo Todd M. Austin Page 20