LIU SPS Low level RF Slip stacking implementation Arthur Spierer, - - PowerPoint PPT Presentation

LIU – SPS Low level RF

Slip stacking implementation

Arthur Spierer, 18.04.2018

SPS LLRF overview

IOT

Cavity Controller

Beam Control SPS RF-Synchro

coaxial

Beam TWC800 SPS Tunnel Σ Σ Σ TWC800 TWC200 Σ TWC200

Fibers to/from LHC

Surface building BA3 (faraday cage)

coaxial cable waveguide

IOT

Cavity Controller coaxial waveguide

TX

Cavity Controller coaxial Coaxial line

TX

Cavity Controller coaxial Coaxial line Radial Pick-up(s) Phase Pick-up(s)

Surface building BA3

WR RX TX WR RX TX

Radial position

TX WR

Beam phase

TX 2x WR

WR Switch

WR

FTWs, Setpoints

RX RX RX TX WR WR WR

frev

CPS RF-synchro

WR

FREVinj FRFinj Fibers to kickers

Ref magnet B-field

WR ADC

δRbeam ΔΦ(RF, RF ext )

RF Diagnostic

WR

frev fRF

RF Obs triggers

6x

Fibers to/from CPS FC, EXT FRF, EXT (BQM, MR, ...)

RX TX RX TX

Ibeam dV, dP

RX TX RX TX

≥ 13 Fibers to BA2

fRF WCM

Ibeam, φbeam

coaxial

1.25Gbps >4Gbps >4Gbps 2 >5Gbps coaxial 8

WR Switch

WR B-field 1.25Gbps Master clock 10MHz TDC

ΔT(frev ,fC ext)

fC,ext fRFext

coaxial 8x Σ Vcav 4

Beam control Hardware overview

AFCZ FMC Carrier 16 SFP+ RTM

Beam Phase/Pos. Cavity Controllers

Zynq

RTM AMC eRTM

White-rabbit receiver «LO» PLL Cleaning PLL clock

Digital I/O’s 4x ADC

125Msps

SFP SFP SFP SFP QSFP QSFP QSFP

WR RF network WR B network

Cavity Controllers Beam Phase/Pos.

FMC FMC

Timings

External RF 400 MHz

External Fcommon

Cavity controller overview

SIS8300-KU (Desy/Struck) DS8VM1 (Desy/Struck)

Beam Control

Beam Control AFCZ

Blow up noise Phase loop Radial loop Synchro loop

Σ

NCO Timing RF White Rabbit Frequency program Longitudinal damper ADC FMC Digital I/O FMC B-train White Rabbit

FTWs ΦH1, prog, b1-2 ΦH1, b1-2

Serial links

ΔTFc,Frev ΔΦRF,RFext B, Bdot Vcav Φbeam dV, dP dRprog ΔFTWrev,sync, b1-2 dR ΔFTWrev,radial dRprog FTWrev,prog, b1-2 Φs VcavIQ Φbeam ΔFTWrev,phase, b1-2

Backplane LVDS Function generator

Vca

v[0..7]

Φca

v[0..7]

Timings

B-train WR switch CTRx Fc, Frev distribution FRF, External distribution Beam radial position Beam phase 8x Cavity controlers CTRx RF WR switch

dR Φbeam Vcav dV, dP FRF,ext Fc ΔFTWnoise FTWs Φs

Memory Map

ΦH1 Φbeam ΦH1,prog Frev b1-2 dRprog

Hardware unit FPGA firmware FPGA CPU

Legend

Beam Control Slip Stacking

• Slip Stacking is part of the frequency program
• Frequency and voltage ramps are computed in real-time or recorded
• Two phase loops and synchro loops during Slip Stacking
• Bunch by bunch phase measurement for each super-batch
• NCOs are synchronised and updated through White-Rabbit

Cavity controller group 1 Cavity controller group 1 Beam Control AFCZ

Phase loop Synchro loop

Σ

NCO RF White Rabbit Frequency program B-train White Rabbit

FTW ΦH1, prog, b1-2 ΦH1, b1-2

Serial links

B, Bdot ΔFTWrev,sync, b1-2 FTWrev,prog, b1-2 Φs VcavIQ Φbeam ΔFTWrev,phase, b1-2

B-train WR switch Beam phase RF WR switch

Φbeam FTW ΦH1, b1-2 Φbeam ΦH1,prog, b1-2 Frev b1-2 Hardware unit FPGA firmware FPGA CPU

Legend

Cavity controller group 1

RF White Rabbit NCO

ΦH1, b1 Frev b1 AM ΦH1, b1-2 FTWdelayed FTWdelayed

Cavity controller group 1 Cavity controller group 1

Cavity controller group 2

RF White Rabbit NCO

ΦH1, b1 Frev b1 AM FTWdelayed

Frequency Program Slip Stacking

• Ramps are computed (real time or recorded) based on parameters
• Maximum slope, Target frequency, Maximum frequency offset, …
• The slippage can be monitored in real time for the two super-batches
• Allows detection of the recapture time

Frequency Program

ΔTFc,Frev ΔΦRF,RFext B dRprog Φs FTWrev, prog, b1-2 Stable Phase B to Frev Rephasing Slip Stacking Bdot Vrf Ftarget,dFmax, dFmax_slope, µpll

Fprog

m/q, γt, RSPS, HSPS, Finf Frev

FTWrev ΔFreph. ΔFslip,b1-2

Transcross dFtarget,dFmax, dFmax_slope ΦH1, b1-2

Real time computation

• Allows a turn by turn resolution without interpolation
• Straight forward for frequency, to be studied for voltage

Slip Stacking

Ramp Timer Sequencer parameters dFtarget,dFmax

, dFmax_slope

ΔFslip,b1-2 startslip Frevb1-2

mode t

FTWrev_prog

constants Trev_prog done

ΦH1, b1-2 ΔΦslip

• SPS Rephasing trim function
• Trim functions are symmetrical for each cavity group

Frequency trim function candidate

t f Dt/2

• Dt/2

Df/2

• Df/2

slope a

3 2 3 3 4

3 2 . ) ( t f a t a t f Δ − =

Voltage trim function

• Voltage function is
• Derived from the frequency ramp and …
• Meant to keep a constant bucket filling factor

Amplitude modulation

• Each cavity group RF is amplitude modulated (ON/OFF)
• To separate the two super-batches injected at the same frequency
• To decrease interferences between group 1 & 2 RF and batches
• Once the super-batches are too close, RF is kept ON

Time Trev1 Cavity group 1 RF on Tba φH1 Tba Tba Ton Cavity group 2 RF on φH1 φon2 φoff2 φon1 φoff1 Tfill Tba

Frequency Tuning Words transmission

• Using White Rabbit link
• Keep all nodes synchronised
• Fixed Latency
• One update per turn

Name Size (bits) Description FTW_H1 48 FTW Harmonic 1 main FTW_H1[0..7] 8x48 FTW Harmonic 1 for each cavity FTW_ON 49 FTW when RF is on during Fixed frequency Acceleration (Ions) OFFSET_H1 48 Offset on H1 phase Vcavity[0..7] 8x2x16 Cavity voltage setpoint in Amp/phase or IQ Control Status 16 Control and status: bit 0: NCO_rst bit 1: trigger capture bit 2: NCO modulation on/off bit 4-3: NCO modulation rate Phase_H1 48 Current H1 phase in beam control for synchronisation check

Numerically Controlled Oscillator (NCO)

• Reset and updated synchronously in every nodes
• Runs with the same clock on every nodes
• Phase comparator for amplitude modulation

HRF FTWLO FTWH1

Azimuth detection

FREV Accumulator

D Q

φH1 φH1 φIF,FSK

± FTWFSK FTWIFavg

nco_rst

1 H FSK

FTW FTW φFSK,cor

FIF,avg Accumulator

D Q

FFSK Accumulator

D Q

φFSK,cor FTWRF,ON

x(-1)

cordic

cos(ωIF) sin(ωIF)

φIFavg

Phase Loop

• Two independent phase loops
• Bunch mask for averaging on each super-batch
• Stopped when batches start to superpose
• Readings of the bunch per bunch phase are not coherent when the

batches are superposed

• No phase loops
• Can help defining recapture time

LHC ion cycle