LibreSilicon - Breaking the microchip monopoly leviathanch | - - PowerPoint PPT Presentation

▶
libresilicon breaking the microchip monopoly
SMART_READER_LITE
LIVE PREVIEW

LibreSilicon - Breaking the microchip monopoly leviathanch | - - PowerPoint PPT Presentation

Sep 28, 2022 280 likes •1.2k views

Introduction Standard cells Silicon compiler Process Epilog LibreSilicon - Breaking the microchip monopoly leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly Introduction Standard cells Silicon

slide-1
SLIDE 1

Introduction Standard cells Silicon compiler Process Epilog

LibreSilicon - Breaking the microchip monopoly

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-2
SLIDE 2

Introduction Standard cells Silicon compiler Process Epilog

The LibreSilicon project

In 2017 leviathan already has found a clean room to rent at Hong Kong University

  • f Science and Technology

Last year at 34c3 he gave a Lightning Talk about LibreSilicon Since then we’re meeting every week on Sunday 2100 HKT at Mumble Communicating, planing and working via mailing list and Mumble Held a tool chain hackathon end of May 2018 Already two of us got qualifjcation for clean room access at HKUST Processing our fjrst test wafer for characterization (→ pics follow)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-3
SLIDE 3

Introduction Standard cells Silicon compiler Process Epilog

Basic points

Starting with 1µm ”feature size” because still well documented in text books Robust, at least 5 Volt tolerant, well suited for maker, tinkerer and hacker Twin-Well process for CMOS with 3 metal layer w/ very interesting additions Quite suitable for ”low tec” in the basement For analog circuits, regarding their huge transistor sizes, small feature sizes do not matter

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-4
SLIDE 4

Introduction Standard cells Silicon compiler Process Epilog

Main (re-)construction areas

1 Figure out / develop the process itself (→ almost done) 2 Rebuild / modernize the tools / design fmow (→ ongoing) 3 Compile / design a almost complete standard cell library (→ ongoing) leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-5
SLIDE 5

Introduction Standard cells Silicon compiler Process Epilog

Standard Cells

Standard Cells are usualy A collection of some dozens of combinatorial + sequential cells Instantiated many, many times in a netlist Used also as layout primitives

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-6
SLIDE 6

Introduction Standard cells Silicon compiler Process Epilog

Typical cells

AND4 NAND3 NAND2 EQ2 OR4 NOR3 NOR2 XOR2 INV S R Q SRL D C Q DFF J K C Q JKFF ... and much more

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-7
SLIDE 7

Introduction Standard cells Silicon compiler Process Epilog

Design goals

here are Being almost complete (more cells → better netlist) Being low energy consuming (less Watts per square) Being as fast as possible (w/ small timing delay) Having a small footprint (small cell size) Well, does not fjt all together well.

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-8
SLIDE 8

Introduction Standard cells Silicon compiler Process Epilog

Cell representations

every single cell needs difgerent representation for working smooth with difgerent tools, e.g. For simulation (→ Verilog and Spice) For synthesis (→ Liberty fjle format) For timing (→ standard delay format) For layout (→ library exchange format) Or, even for dedicated tools (e.g. Magic) And documentation (schematics, truth tables, data sheets, ..)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-9
SLIDE 9

Introduction Standard cells Silicon compiler Process Epilog

Cell representations

Regarding our goal of several hundreds cells (estimated 300+), generating all cell representations, becomes a huge task. Nobody likes to do this manually. We need a tool for that! A cell generator.

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-10
SLIDE 10

Introduction Standard cells Silicon compiler Process Epilog

Cell generator

This cell generator, named ”Popcorn”, is still work-in-progress. Starting from one source this tool Should generate all representation formats Already helps drawing the schematics Already generates a couple of data sheet like LaTeX fjle Was written in Tcl fjrst, but Needs a rewrite in a more sophisticated / AI-ish language Now when test wafer characterization is done

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-11
SLIDE 11

Introduction Standard cells Silicon compiler Process Epilog

Standard cell library

https://www.github.com/chipforge/StdCellLib (→ repository) https://vcs.in-berlin.de/chipforge_stdcelllib/index (→ wiki) maintained by chipforge

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-12
SLIDE 12

Introduction Standard cells Silicon compiler Process Epilog

Open source tools

yosys graywolf qrouter several FPGA routers

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-13
SLIDE 13

Introduction Standard cells Silicon compiler Process Epilog

graywolf

Originates in academia: TimberWolf Simulated annealing

Meta heuristic that is useful not only for placement

Inline syscalls

This is just a bad idea

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-14
SLIDE 14

Introduction Standard cells Silicon compiler Process Epilog

qrouter

Started in 2011 by Tim Edwards Widely used for FPGA

Not ready for silicon

Sequential routing

Parallelism not in scope

Diffjcult to prove formal correctness

Prove that C implementation of rip-up and re-route is correct

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-15
SLIDE 15

Introduction Standard cells Silicon compiler Process Epilog

Productive tools

Difgerent tool sets like BonnRoute, Cadence suite, Alliance tools, etc. Similar capabilities with respect to silicon Just throw man-power at VLSI — what is automation?

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-16
SLIDE 16

Introduction Standard cells Silicon compiler Process Epilog leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-17
SLIDE 17

Introduction Standard cells Silicon compiler Process Epilog

Routing: State of the art

Place components for a large chip Route wires roughly along a chessboard for a large chip Route detailed tracks and vias for a large chip Formal correctness: Rip-up and Re-route Formal style: Sequential/Imperative code

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-18
SLIDE 18

Introduction Standard cells Silicon compiler Process Epilog

Routing: Proposed

Decomposition for a large chip Place components and route for small chips in parallel Place abstract gates and route recursively Formal correctness: Reduction from SMT Formal style: Parallel/Declarative code

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-19
SLIDE 19

Introduction Standard cells Silicon compiler Process Epilog

Divide and Conquer

Academia + Industry: Placement and Routing are difgerent problems All components map to the same problem LibreSilicon: Placement and Routing are the same problem Difgerent components map to difgerent problems

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-20
SLIDE 20

Introduction Standard cells Silicon compiler Process Epilog

Routing Hierarchy

Academia + Industry: Geographical partitioning of a wafer → cut tree Based on preceeding placement steps LibreSilicon: Modular chip development → subcell hierarchy Subcells carry implicit and explicit subcells

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-21
SLIDE 21

Introduction Standard cells Silicon compiler Process Epilog

Frontier: Parallelism

BonnRoute: concurrency + shared memory model qrouter: none lsc: map + reduce

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-22
SLIDE 22

Introduction Standard cells Silicon compiler Process Epilog

Subcell hierarchies

Explicit subcell hierarchies through high modularization Implicit subcell hierarchies through exlining Preserve hierarchy in compiler interfaces

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-23
SLIDE 23

Introduction Standard cells Silicon compiler Process Epilog

High modularization

https://murmur.libresilicon.com/lsc/rocket-chip-yosys

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-24
SLIDE 24

Introduction Standard cells Silicon compiler Process Epilog

Exlining

https://murmur.libresilicon.com/lsc/rocket-chip-exline

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-25
SLIDE 25

Introduction Standard cells Silicon compiler Process Epilog

Unconstrained Small Unifjed Silicon Problem

Components and nets → rectilinear geometries Components do not overlap Nets overlap with their pins on components

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-26
SLIDE 26

Introduction Standard cells Silicon compiler Process Epilog

Minimizing Goals

Layout area Maximum wire length Via count Crossing number (computational) Wire jogs (minor)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-27
SLIDE 27

Introduction Standard cells Silicon compiler Process Epilog

Satisfjability Modulo Theories

Optimization problems Abstraction from Boolean satisfjability Several solvers implement smtlib2

ABC from University of Berkeley CVC4 from Stanford Boolector from Johannes Kepler University MathSAT from Fondazione Bruno Kessler and DISI-University of Trento Yices from SRI Z3 from Microsoft

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-28
SLIDE 28

Introduction Standard cells Silicon compiler Process Epilog

Boolean Satisfjability

(α1 ∨ α2 ∨ α3) ∧ (¬α4 ∨ α5 ∨ α6)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-29
SLIDE 29

Introduction Standard cells Silicon compiler Process Epilog

Defjning rectangular components

(left, bottom) (right, top)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-30
SLIDE 30

Introduction Standard cells Silicon compiler Process Epilog

Overlaps

(a.left, a.bottom) (a.right, a.top) (b.left, b.bottom) (b.right, b.top)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-31
SLIDE 31

Introduction Standard cells Silicon compiler Process Epilog

Reduction from SMT

a.right − a.left = dimension.x b.right − b.left = dimension.y a.top − a.bottom = dimension.x b.top − b.bottom = dimension.y b.left > a.right ∨ a.left > b.right ∨a.bottom > b.top ∨b.bottom > a.top

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-32
SLIDE 32

Introduction Standard cells Silicon compiler Process Epilog

Combining in the LSC Semigroup

  • verlaps + pin connect + arbitrary constraint

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-33
SLIDE 33

Introduction Standard cells Silicon compiler Process Epilog

Stay low

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-34
SLIDE 34

Introduction Standard cells Silicon compiler Process Epilog

Maximize yield

Minimize area of a chip → silicon compiler Minimize physical errors → silicon process

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-35
SLIDE 35

Introduction Standard cells Silicon compiler Process Epilog

Libre Silicon Compiler

https://www.github.com/foshardware/lsc (→ repository) maintained by foshardware

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-36
SLIDE 36

Introduction Standard cells Silicon compiler Process Epilog

Why Hong Kong?

History

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-37
SLIDE 37

Introduction Standard cells Silicon compiler Process Epilog

Why Hong Kong?

Nano fabrication facility

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-38
SLIDE 38

Introduction Standard cells Silicon compiler Process Epilog

Why Hong Kong?

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-39
SLIDE 39

Introduction Standard cells Silicon compiler Process Epilog

Why Hong Kong?

Conclusion Advanced labs available for R&D Shenzhen and Hong Kong have fabs which are willing to introduce LibreSilicon Channels for easy export to Europe already established (One belt, one road) Climate is better Payment is better Food is better * is better The sun shines brightest in the east ;-)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-40
SLIDE 40

Introduction Standard cells Silicon compiler Process Epilog

Features

MOSFETs LDMOSFETs (High voltage) BJTs Zener polysilicon diodes SONOS fmash cells Polysilicon resistors Metal caps

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-41
SLIDE 41

Introduction Standard cells Silicon compiler Process Epilog

Process design considerations

Should be portable Robust Low amount of layers KISS (Keep it simple and stupid) Avoid expensive machines Can be manufactured in a home lab

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-42
SLIDE 42

Introduction Standard cells Silicon compiler Process Epilog

Process design considerations

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-43
SLIDE 43

Introduction Standard cells Silicon compiler Process Epilog

Process design considerations

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-44
SLIDE 44

Introduction Standard cells Silicon compiler Process Epilog

Cross section

Silicon substrate Silicon substrate n+ n+ n+ p+

PMOS NMOS SONOS fmash cell (PMOS) NPN BJT PNP BJT Polysilicon diode Polyresistor

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-45
SLIDE 45

Introduction Standard cells Silicon compiler Process Epilog

PearlRiver (珠江芯片一号)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-46
SLIDE 46

Introduction Standard cells Silicon compiler Process Epilog

PearlRiver (珠江芯片一号)

Fulfjlls following functions: Debugging Calibration of new equipment to LibreSilicon Research of new features Syncing process features between fabs

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-47
SLIDE 47

Introduction Standard cells Silicon compiler Process Epilog

Photomask

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-48
SLIDE 48

Introduction Standard cells Silicon compiler Process Epilog

Photomask

Is stepper/aligner brand specifjc ASML stepper masks contain 4 layers each The NFF stepper has a reduction value of 5:1 A 5 micron gate on the mask is 1 micron on the wafer

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-49
SLIDE 49

Introduction Standard cells Silicon compiler Process Epilog

Photo resist (HKUST)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-50
SLIDE 50

Introduction Standard cells Silicon compiler Process Epilog

Photo resist (HKUST)

Two types of photo resist: FH 6400L (implantation) HPR 504 (normal etch) Factors to consider: Thickness of FH 6400L and implantation energy are interlinked Thickness of HPR 504 and etching time are interlinked (selectivity)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-51
SLIDE 51

Introduction Standard cells Silicon compiler Process Epilog

After exposure

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-52
SLIDE 52

Introduction Standard cells Silicon compiler Process Epilog

Alignment

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-53
SLIDE 53

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-54
SLIDE 54

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Wells (nwell/pwell):

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-55
SLIDE 55

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Wells (nwell/pwell):

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-56
SLIDE 56

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Recipe for nwell: Coat with implant resist (soft bake 60 seconds, 110°C) Expose nwell-mask Puddle develop 69 seconds and hard bake 60 seconds at 120°C Implant Phosphorus, 2.33 × 1012cm−2 @ 70keV Strip resist with plasma asher or 20 minutes in 120°C hot sulfuric acid Note: Alternatively predisposition can be used

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-57
SLIDE 57

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Recipe for pwell: Coat with implant resist (soft bake 60 seconds, 110°C) Expose pwell-mask Puddle develop 69 seconds and hard bake 60 seconds at 120°C Implant Boron, 1.93 × 1012cm−2 @ 40keV Strip resist with plasma asher or 20 minutes in 120°C hot sulfuric acid Difguse both wells together for 4 hours at 1050°C in inert atmosphere (N2) Note: Alternatively predisposition can be used

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-58
SLIDE 58

Introduction Standard cells Silicon compiler Process Epilog

The Fick’s equation ∂N ∂t = D · ∂2N ∂x2

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-59
SLIDE 59

Introduction Standard cells Silicon compiler Process Epilog

The Fick’s equation

xl(t) = 2 · √De · t = 2 · √ D0 · exp ( − Ea

k·T

) · t Element D0 [

cm2 s

] Ea [eV] P 10.50 3.69 As 0.32 3.56 Sb 5.60 3.95 B 10.50 3.69 Al 8.00 3.47 Ga 3.60 3.51 Cu 0.0025 0.65

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-60
SLIDE 60

Introduction Standard cells Silicon compiler Process Epilog

The Fick’s equation

N(x, t) =

Q √π·De·t · exp

(

−x2 4·De·t

)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-61
SLIDE 61

Introduction Standard cells Silicon compiler Process Epilog

The Fick’s equation

For the concentration within the channel may x = 0 This results in the concentration at the surface (around 100nm deep ≪ 2 microns) N =

Q √π·De·t

Or the implant dosage: Q = N · √π · De · t

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-62
SLIDE 62

Introduction Standard cells Silicon compiler Process Epilog

The Fick’s equation

Fixed source difgusion: xj = 2 · √ D · t · ln (

N0 NB

)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-63
SLIDE 63

Introduction Standard cells Silicon compiler Process Epilog

Threshold calculation

PMOS

Silicon substrate N-Well n+ p+ p+ Source Gate Drain

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-64
SLIDE 64

Introduction Standard cells Silicon compiler Process Epilog

Threshold calculation

PMOS |ϕF| = VT ln Nd ni (1) VT = VFB − 2 · |ϕF| − √ 2 · ϵs · q · Nd · (2 · |ϕF| − VSB) Cox (2) VFB = − (Eg 2 − ϕF ) − QSS Cox (3)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-65
SLIDE 65

Introduction Standard cells Silicon compiler Process Epilog

Threshold calculation

NMOS

Silicon substrate P-Well p+ n+ n+ Source Gate Drain

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-66
SLIDE 66

Introduction Standard cells Silicon compiler Process Epilog

Threshold calculation

NMOS ϕF = VT ln Na ni (4) VT = VFB + 2 · ϕF + √ 2 · ϵs · q · Na · (2 · ϕF + VSB) Cox (5) VFB = − (Eg 2 + ϕF ) − QSS Cox (6)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-67
SLIDE 67

Introduction Standard cells Silicon compiler Process Epilog

SONOS fmash

Stands for Silicon Oxide Nitride Oxide Silicon

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-68
SLIDE 68

Introduction Standard cells Silicon compiler Process Epilog

SONOS fmash

SONOS NMOS

Silicon substrate P-Well p+ n+ n+ Bulk Source Gate Drain

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-69
SLIDE 69

Introduction Standard cells Silicon compiler Process Epilog

SONOS fmash

SONOS NMOS Programming/Erasing happens by changing QSS A variation of QSS shifts the threshold voltage QSS can be changed by applying an enough high voltage between bulk and gate (approx. 20 V) High enough voltage tunnels electrons into the nitride Shifting the threshold voltage away from 0.8 V / -0.8 V makes it stay turned ofg when a ”1” is applied

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-70
SLIDE 70

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Isolation (STI):

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-71
SLIDE 71

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Isolation (STI):

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-72
SLIDE 72

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Recipe for STI: Dry

Plasma etching recipes are machine specifjc Variate the cycles for your recipe to match 2 microns

Wet

Take TMAH: N(CH3)+

4 OH− (Tetramethylammonium hydroxide)

Dilute with deionized water with DI:TMAH (3:1) Heat TMAH (25%) to 80°C Dip wafer into the solution for around 6 minutes and 15 seconds (320nm/min, 2 microns)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-73
SLIDE 73

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Metal interconnect (metal1):

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-74
SLIDE 74

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Metal interconnect (metal1):

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-75
SLIDE 75

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Recipe for metal interconnects: Make a vacuum (low pressure) Deposit 100nm Aluminum Deposit 30nm Titanium over the Aluminum Take out of vacuum Dip into HF:DI (1:10) water solution for a few seconds until Titanium is gone Dip into FeCl3 or other suitable Aluminum etchant for around 30 seconds until Aluminum is gone

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-76
SLIDE 76

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation materials Low temperature oxide (LTO) Phosphosilicate glass (PSG) Can both be wet or dry etched

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-77
SLIDE 77

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation conceptional

Silicon substrate Silicon substrate n+ n+ n+ p+

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-78
SLIDE 78

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation layout

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-79
SLIDE 79

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation in reality

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-80
SLIDE 80

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-81
SLIDE 81

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-82
SLIDE 82

Introduction Standard cells Silicon compiler Process Epilog

Example: NOR3 ring oscillator

Passivation/Isolation 1 micron is not enough 2 more microns need to be deposited Can be then be etched with BOE after exposure and development

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-83
SLIDE 83

Introduction Standard cells Silicon compiler Process Epilog

Process

https://www.github.com/libresilicon/process (→ repository) maintained by leviathanch

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-84
SLIDE 84

Introduction Standard cells Silicon compiler Process Epilog

Next

Victor and I

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-85
SLIDE 85

Introduction Standard cells Silicon compiler Process Epilog

Next

We will

1 Finish debugging all the features of PearlRiver (珠江芯片一号) 2 Create preliminary Verilog and Spice models 3 Autogenerating standard cells with Popcorn scripts 4 Building ADCs/DACs and much more analog stuff 5 Build the North Point MCU (北⻆芯片) 6 Build the Sau Mau Ping SoC (秀茂坪芯片) leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-86
SLIDE 86

Introduction Standard cells Silicon compiler Process Epilog

Next

With lots of luck from the goddess

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-87
SLIDE 87

Introduction Standard cells Silicon compiler Process Epilog

North Point (北⻆芯片)

Features RISC-V core based on RV32EAC ISA Pin compatible to ATMega8 Same features as ATMega8 Tolerates up to 40V

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-88
SLIDE 88

Introduction Standard cells Silicon compiler Process Epilog

North Point (北⻆芯片)

Survey https://survey.libresilicon.com

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-89
SLIDE 89

Introduction Standard cells Silicon compiler Process Epilog

Future

Equipment we are using is ready for going down to 500 nm (→ 2 nodes shrinking) :-)

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-90
SLIDE 90

Introduction Standard cells Silicon compiler Process Epilog

Request for Chips

Which Free and Open Silicon do you like to see also? More Analog Stufg? (→ NE555?, uA741?) More Digital Stufg? (→ CD4000-series? LISP-CPU?) More Mixed-Signal Stufg? (→ SoC w/ Analog-Digital / Digital-Analog Converter?) ? Keep on track, let us know your wish list! Mailing List: http://list.o2s.ch/mailman/listinfo/libre-silicon-devel

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly

slide-91
SLIDE 91

Introduction Standard cells Silicon compiler Process Epilog

Thanks!

非常感谢你们! Thank you very much! Vielen herzlichen Dank!

leviathanch | chipforge | foshardware (Lanceville Technology) Breaking the microchip monopoly