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LCCC 2011 An Adaptive Wide-Area Power System Damping Controller using Synchrophasor Data Scott G. Ghiocel and Joe H. Chow Rensselaer Polytechnic Institute Electrical, Computer, and Systems Engineering Department May 18-20, 2011 Outline


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SLIDE 1

LCCC 2011 An Adaptive Wide-Area Power System Damping Controller using Synchrophasor Data

Scott G. Ghiocel and Joe H. Chow

Rensselaer Polytechnic Institute Electrical, Computer, and Systems Engineering Department

May 18-20, 2011

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SLIDE 2

Outline

Overview of power system electromechanical mode damping controllers Synchrophasor data as inputs to damping controllers

1

Synchrophasor data latency

2

Geographical coverage

3

Data loss

An adaptive damping controller

1

Latency-based controller switching

2

Phase compensation design

A design example of a Thyristor-Controlled Series Compensator (TCSC)

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SLIDE 3

Power System Electromechanical Mode Oscillations

1 Electromechanical modes are the oscillations of the multiple

generator inertias against each other through the electrical network

2 Three types of electromechanical modes 1

Intraplant modes: 2-3 Hz

2

Local mode: 1-2 Hz

3

Interarea modes: 0.2-0.6 Hz

A simple power system showing a local mode and an intraplant mode

L

jX

e

P

Transmission line

T

jX Transformers Generators Infinite bus

T

jX Local mode Intraplant mode

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SLIDE 4

Interarea mode: Klein-Rogers-Kundur 2-area, 4-machine system

Local mode Interarea mode Local mode 1 2 3 13 12 11 Gen 1 Gen 2 Gen 11 Gen 12

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SLIDE 5

US Western System Breakout - August 10, 1996 John Hauer

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SLIDE 6

Nordic System Kjetil Ulhen

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SLIDE 7

Nature of Network Oscillations

The 2008 Florida Disturbance

!"#$"%& '"()*+,,#

  • "#.,/

0##1*2+"* 34567"8&+1"*

  • )%&(

f propagation: Duval → Volunteer → Cordova → Dorsey → Orrington

5 10 15 20 25 30 35 40 45 50 59.75 59.8 59.85 59.9 59.95 60 60.05 60.1 60.15 60.2 60.25

Time in seconds with origin at: 26/02/2008 − 18:08:53h Frequency (Hz)

Orrington Duval Dorsey Cordova Volunteer 15 20 25 30 59.75 59.8 59.85 59.9 59.95 60 60.05 60.1 60.15 60.2

Time in seconds with origin at: 26/02/2008 − 18:08:53h Frequency (Hz)

Orrington Duval Dorsey Cordova Volunteer

  • L. Vanfretti

(RPI-ECSE) PhD Candidacy Exam December 3rd, 2009 40 / 67

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SLIDE 8

US Eastern Interconnection, Florida event, February 26, 2008 Luigi Vanfretti

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SLIDE 9

Electromechanical Model Damping Controllers Power system stabilizers (PSS): provides damping signal via the voltage regulator summing junction; mostly for local mode damping, but also beneficial to interarea modes; PSS design focuses on phase-lead compensation; US WECC requires PSS on every generating unit/cluster greater than 30/70 MVA. Speed-input PSS

s

V

+1

w w

T s T s

max s

V

f

Washout filters Lead-lag compensator

1 3 PSS 2 4

1 1 1 1 sT sT K sT sT ! ! ! ! Filtered speed

min s

V (5-10%) (-5-10%) 10sec

w

T "

Integral of accelerating power PSS

Lowpass filter

2 2 Hs Hs ( ) G s ( ) s ! ( )

e

P s ! ( )

m

P s !

"

2 2

( ) ( +1)

w w

T s T s

Washout filters

( ) s 1 2Hs

2 2

( ) ( +1)

w w

T s T s ( )

e

P s

' ( ) m

P s !

"

8 9

1 (1 )

N M

T s T s # $ % & % & % & % & % ' (

' acc( )

P s !

"

)

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SLIDE 10

Flexible AC Transmission Systems (FACTS) Controllers High-voltage, high-power power-electronic switches to provide reactive power support and provide interarea damping control. (a) Shunt controllers: static var compensator (SVC), static synchronous compensator (STATCOM) (b) Series controllers: thyristor-controlled series compensator (TCSC), static synchronous series compensator (SSSC) (c) Coupled controllers: unified power flow controller (UPFC), interline power flow controller (IPFC), back-to-back (B2B) STATCOM

Thyristor switches

I ( ) ( )

C L

I I I ! L C ( )

L

I

" !

( )

C

V

Thyristor switches

(a) SVC schematic (b) TCSC schematic

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SLIDE 11

VSC-based FACTS Controllers

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SLIDE 12

Interarea Mode Damping using Shunt and Series FACTS Controllers

1 As FACTS controllers are located in power transfer paths between

two areas, supplementary signals Vs can be used in FACTS Controllers to enhance interarea damping.

2 Machine speeds are normally not available to FACTS controllers,

because they are not located next to generator buses. Thus a FACTS controller would need to use other signals that are available locally, or sometimes, remotely.

(b) TCSC control loop

ref

V

V

! "

A

K

1

A

T

SVC

B

Anti-windup limits s

V

! "

1

A A

K sT ! TCSC

X

Anti-windup limits s

V

(a) SVC control loop

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SLIDE 13

Candidate Damping Control Input Signals for SVC/TCSC

1 Local bus voltage magnitude V 2 Local bus frequency f 3 Active power transfer P 4 Active component of line current Ia 5 Line current magnitude Im 6 Synthesized angular difference between two areas 7 Remote bus voltage or machine angles as measured by phasor

measurement units

Selection criteria

The observability of the interarea mode in the signal should be high (the interarea mode should be clearly visible or no zeros near the interarea mode). The damping controller should be robust with respect to changes in power transfer direction and line impedance.

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SLIDE 14

Synthesized angle difference between two areas

1 Use local voltage and current measurements to extrapolate to the

“center-of-angle” of remote coherent areas.

Area 1

m

I

1syn 1 1syn m m

V V Z I !

1m

V

TCSC Area 2

2m

V

2syn 2 2syn m m

V V Z I "

2 With the availability of synchrophasor measurements, the

“center-of-angle” can be directly measured and communicated to the controller.

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SLIDE 15

PMU Data Communication Path

High-voltage Substation 3-phase currents and voltages Phasor Measurement Unit Local Phasor Data Concentrator Central Phasor Data Concentrator Damping Controller GPS Signal GPS Signal PMU data PMU data Internet

PMU data are time stamped with GPS clock signal A typical architecture with local PDCs sending PMU data to a central/regional PDC Latency due to PMU signal processing, data transmission (UDP

  • r TCP/IP), and data concentration

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SLIDE 16

Latency Estimate of Hydro Quebec WACS From Charles Cyr and Innocent Kamwa (HQ) PMU filter delay 73 ms Local data concentration 16 ms 2,000 km in optical fiber 10 ms Central data concentration 10 ms Total estimated latency 109 ms Longest delay is PMU data processing of current and voltage phasors - to reduce noise, magnitude and phase of a single phase are estimated over a 1-2 cycles (sometimes even longer) data window. Transmission propagation time - 1,000 km of dedicated optical fiber: UDP 5 ms; TCP/IP 15 ms Impact of latency for interarea mode damping - a 150 ms latency for an oscillation of period 2 sec is like a phase lag of 0.150/2 × 360◦ = 27◦

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SLIDE 17

Geographical Coverage of PMU Data PMUs are mostly located on high-voltage transmission buses, not at generator terminals, although neighboring PMUs can estimate generator terminal quantities Generator rotor angles and speeds not included in PMU data - the aggregate machine rotor angle δa and speed ωa can be calculated using the Interarea Model Estimation method. Beneficial to use a weighted sum of PMU variables, such as the weighted average of the bus voltage angles in a coherent area θa =

Na

  • i=1

αiθi (1) where Na is the number of buses, and the αi’s are selected to eliminate the local mode components in θa.

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SLIDE 18

PMU Data Loss PMU data loss

a PMU not in service loss of GPS signal reception communication network congestion

A phasor data concentrator (PDC) assembles PMU data from time stamps.

Time-out function - PMU data not arriving within a specified time will be dropped

Two prototype PMU systems in Brazil reported 0.01% to 14% data loss during peak internet traffic periods. If an input signal consists of several PMU measurements, like θa, it can still be constructed if one of the component PMU data is lost.

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SLIDE 19

Control Schemes Accounting for Input Signal Latency Control of delayed system has been studied by control community for many years. Recent interests in power system community, typically related to use of remote signals requiring data transmission Sometimes remote signals are used to complement local signals to remove unfavorable zeros. Stahlhut et al. studied the impact of latency on electromechanical mode damping. Chaudhuri, Ray, Majumder, and Chaudhuri proposed a forward phase rotation in the time domain to compensate for latency.

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SLIDE 20

Adaptive Control Scheme

( , )

c d

G s T

u y

PMU data queue new PMU data

with delay

d

T 2 main components

1 Latency monitoring: continuously monitor the latency Td of

arriving PMU data by comparing the time stamp with the GPS clock signal.

2 Use Td to determine the controller Gc(s, Td), which is a set of

controllers to provide phase compensation for Td = Td1, Td2, ....

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SLIDE 21

Adaptive Control Algorithm At time t = tk, where t is the time at the controller Gc(s, Tdi) is used for t = tk + ∆t, where ∆t is the sampling period of the PMU data if data is already in buffer, or the incremental time of arrival of the next data point for empty buffer if Td > Tdi, switch to a new controller with the lowest latency Tdj > Td elseif the maximum latency of all the data in the last Tr sec is less than Tdj < Tdi, switch to Gc(s, Tdj) else continue with the same controller end End algorithm

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SLIDE 22

Illustration of the Delay Selection Algorithm

10 20 30 40 50 60 70 80 100 150 200 250 300 350 Time (s) Delay (ms) Signal delay Controller delay

Latency level starts at 150 ms, in increments of 50 ms PMU data arrival (i.e., latency) is modeled as a Poisson process with a minimum total latency of 100 ms Latency increase is on fast time-scale; latency decrease is on slow time-scale to avoid controller transients and potential instability.

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SLIDE 23

Phase Compensation Design Classical 2-stage lead-lag compensators: gain K and time constants Ti, i = 1, ..., 4, can be made dependent on Td Gc(s, Td) = K(Td)1 + T1(Td)s 1 + T2(Td)s 1 + T3(Td)s 1 + T4(Td)s Tws 1 + Tws (2) Let phase compensation at the interarea mode without input signal latency be θcomp For input signal with latency Td, the new phase compensation is θcomp + θ(Td)

For PSS, θcomp is a lead compensation. Thus θcomp + θ(Td) means more lead compensation. For FACTS controllers, θcomp is a lag compensation. Thus θcomp + θ(Td) means less lag compensation, at least for small Td.

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SLIDE 24

Design Illustration 2-area, 4-machine system, adapted from Klein, Rogers, and Kundur

120 Area 2 1 20 3 13 12 11 Gen 1 Gen 2 Gen 11 Gen 12 Area 1 101 110 2 10 4 14 Load 4 Load 14 999 201 202

At 400 MW of power transfer, the interarea mode at 0.0230 ± j4.119 is unstable. Local modes: −0.6327 ± j7.0378 and −0.5698 ± j7.2802. The TCSC is used to damp the interarea oscillations between the 2 areas.

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SLIDE 25

TCSC Input Signals and Effectiveness Input signal Zeros close to the interarea mode Vm201 (local) 0.379 ± j2.19 Vm101 none Vm13 0.126 ± j5.09 Im(201−202) (local) 0.0311 ± j3.80 θ3 − θ13 −0.0786 ± j5.63 0.5(θ1 + θ2) − 0.5(θ11 + θ12) none (used as input signal) 0.5(δ1 + δ2) − 0.5(δ11 + δ12) −0.125 + j1.99 0.5(ω1 + ω2) − 0.5(ω11 + ω12) none Vm denotes the bus voltage magnitude, Im the line current magnitude, θ the bus voltage angle, δ the machine angle, and ω the machine speed. The number in the subscript of these variables denotes either the bus number or the machine number.

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SLIDE 26

Root-Locus Analysis - Without Latency

−8 −7 −6 −5 −4 −3 −2 −1 1 2 2 4 6 8 10 Root Locus Real Axis Imaginary Axis −8 −7 −6 −5 −4 −3 −2 −1 1 2 2 4 6 8 10 Root Locus Real Axis Imaginary Axis

(a) (b) Root-locus plots: (a) no phase compensation, (b) with phase-lag compensation

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SLIDE 27

Damping Controller Performance TCSC damping control performance with no data latency, a three-phase short circuit fault on Bus 999 at t = 0.1 sec, cleared in 3 cycles by removing Line 4-999

1 2 3 4 5 6 7 8 9 10 0.94 0.96 0.98 1 1.02 V3 Voltage Magnitude(p.u.) 1 2 3 4 5 6 7 8 9 10 0.1 0.2 0.3 0.4 0.5 Time (s) Angle Diff. (rad) Angle Difference (Input) Signal with TCSC without TCSC with TCSC without TCSC JHC (RPI)

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SLIDE 28

Root-Locus Analysis - With Latency

−8 −7 −6 −5 −4 −3 −2 −1 1 2 2 4 6 8 10 Root Locus Real Axis Imaginary Axis −8 −7 −6 −5 −4 −3 −2 −1 1 2 2 4 6 8 10 Root Locus Real Axis Imaginary Axis

(a) (b) Root-locus plots: (a) phase compensation for latency, (b) no phase compensation for latency Phase compensation θ(Td) for Td = 150 ms: 0.150/(2π/4.119) × 360◦ = 35.4◦ (3)

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SLIDE 29

TCSC Damping Controller with Latency Compensation Gc(s, Td) = K(Td)1 + T1(Td)s 1 + T2(Td)s Tws 1 + Tws (4) where Tw = 10 sec

Table: Adaptive phase compensation (preliminary) Latency Controller T1(Td) T2(Td) ms ms ms compensation Td1 = 150 Gc150(s) 0.1085 0.5425 −42◦ Td2 = 200 Gc200(s) 0.1401 0.4202 −30◦ Td3 = 250 Gc250(s) 0.1716 0.3431 −19.5◦ Td4 = 300 Gc300(s) 0.2050 0.2871 −9.6◦

K(Td) has to be set accordingly to achieve the appropriate damping.

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SLIDE 30

TCSC Controller Response with Latency Compensation

1 2 3 4 5 6 7 8 9 10 0.94 0.96 0.98 1 1.02 V3 Voltage Magnitude(p.u.) 1 2 3 4 5 6 7 8 9 10 0.1 0.2 0.3 0.4 0.5 Time (s) Angle Diff. (rad) Angle Difference (Input) Signal Undelayed Signal Delayed Signal Controller Input 1 2 3 4 5 6 7 8 9 10 0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 Xeq Time (s) Reactance (p.u.)

(a) (b) TSCS performance plots: (a) controller performance, (b) control action

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SLIDE 31

An Expanded Look

1 2 3 4 5 6 7 8 9 10 0.94 0.96 0.98 1 1.02 V3 Voltage Magnitude(p.u.) 1 2 3 4 5 6 7 8 9 10 0.1 0.2 0.3 0.4 0.5 Time (s) Angle Diff. (rad) Angle Difference (Input) Signal Undelayed Signal Delayed Signal Controller Input

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SLIDE 32

Conclusions An adaptive control scheme for an interarea damping controller to counter the variable PMU data latency

a controller switching algorithm based on the latency of PMU data a phase compensation design of the controller for a given set of latency

Algorithm illustrated for a TCSC Future work – apply the adaptive control algorithm to PSSs.

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