Integrated packaging allows for improvement in switching - - PowerPoint PPT Presentation

Integrated packaging allows for improvement in switching characteristics of silicon carbide devices

Cyril BUTTAY1, Khalil EL FALAHI1, Rémi ROBUTEL1, Stanislas HASCOËT1, Christian MARTIN1, Bruno ALLARD1, Mark JOHNSON2

1 Laboratoire Ampère, Lyon, France 2 University of Nottingham, UK

22/5/14

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Outline Introduction Analysis of the switching cell Design improvements Integration of the gate driver Low inductance packaging Integration of common-mode filtering Conclusion

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Outline Introduction Analysis of the switching cell Design improvements Integration of the gate driver Low inductance packaging Integration of common-mode filtering Conclusion

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New components. . .

Millán, J. et al. A Survey of Wide Bandgap Power Semiconductor Devices IEEE transactions on Power Electronics, 2014, 29, 2155-2163

◮ SiC (and GaN) devices are

becoming available;

◮ Faster than Si; ◮ Can manage higher

voltage/current density.

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. . . but old issue

◮ Circuit parasitics cause:

◮ increase in power dissipation; ◮ EMC issues (ringing, common mode);

◮ Investigated for Si IGBTs and MOSFETs:

◮ Power modules with reduced inductance; ◮ Busbar structures; ◮ Development of cabling modelling tools (Q3D, InCa, . . . );

➜ Faster SiC makes it necessary to go further.

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Outline Introduction Analysis of the switching cell Design improvements Integration of the gate driver Low inductance packaging Integration of common-mode filtering Conclusion

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh

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Inverter switching cell

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

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Devices capacitances

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ From 100s of pF to few nF

, but non-linear;

◮ Tend to be larger for SiC than for Si; ◮ Slow down switching; ◮ May oscillate with stray inductances; ◮ Increase power dissipation (charge in control and power

circuits) .

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Gate inductance

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ Slows down switching; ◮ May oscillate with Ciss; ◮ May cause spurious turn-ons if impedance is too high; ◮ Often large (100 nH) because drivers are kept on separate boards.

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Drain inductance

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ The energy stored (1 2LI2) is dissipated in the switches; ◮ May oscillate with Coss, or cause avalanche; ◮ Often relatively large because capacitors are kept on

separate board.

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Source inductance

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ Combines the effects of LG and LD; ◮ Introduces a negative feed-back that opposes (slows-down) turn-on

and turn-off;

◮ Usually small (a few nH), but large consequences due to feed-back; ◮ A small value has a damping effect.

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Output capacitance

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ Offers an alternative (and un-controlled) path to HF signals; ◮ From a few 10s of pF (small copper track on a DBC substrate) up to

several nF (load connected through a shielded cable);

◮ Requires input filtering.

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Outline Introduction Analysis of the switching cell Design improvements Integration of the gate driver Low inductance packaging Integration of common-mode filtering Conclusion

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Design Improvements – Overview

Prototypes designed for high temperature

◮ Active devices:

◮ SiC power devices; ◮ high temperature control electronics;

➜ put control and power on same substrate

◮ Sometimes need for efficient Cooling:

➜ dual-side cooling (sandwich packaging)

◮ Few passive technologies available

◮ fast switching for reduced filtering

➜ integrated filtering for further reduction

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Design Improvements – Overview

Prototypes designed for high temperature

◮ Active devices:

◮ SiC power devices; ◮ high temperature control electronics;

➜ put control and power on same substrate

◮ Sometimes need for efficient Cooling:

➜ dual-side cooling (sandwich packaging)

◮ Few passive technologies available

◮ fast switching for reduced filtering

➜ integrated filtering for further reduction

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Design Improvements – Overview

Prototypes designed for high temperature

◮ Active devices:

◮ SiC power devices; ◮ high temperature control electronics;

➜ put control and power on same substrate

◮ Sometimes need for efficient Cooling:

➜ dual-side cooling (sandwich packaging)

◮ Few passive technologies available

◮ fast switching for reduced filtering

➜ integrated filtering for further reduction

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Design Improvements – Overview

Prototypes designed for high temperature

◮ Active devices:

◮ SiC power devices; ◮ high temperature control electronics;

➜ put control and power on same substrate

◮ Sometimes need for efficient Cooling:

➜ dual-side cooling (sandwich packaging)

◮ Few passive technologies available

◮ fast switching for reduced filtering

➜ integrated filtering for further reduction

Fast switching is attractive for high temperature electronics.

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Integration of the gate driver – 1

◮ Short control loop; ◮ Temperature capability of SOI; ◮ High temp.-rated passives

(>200° C);

◮ High-temp. packaging solutions.

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Integration of the gate driver – 1

◮ Short control loop; ◮ Temperature capability of SOI; ◮ High temp.-rated passives

(>200° C);

◮ High-temp. packaging solutions.

but some “standard” technologies:

◮ Wirebonding; ◮ Hermetic case with long leads.

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Integration of the gate driver – 2

Dead-time Dead-time Level-shifter Buffer Buffer Dead-time Dead-time Level-shifter Buffer Buffer

Vbus OUT GND High-side gate driver Low-side gate driver

Included: Power devices, small DC decoupling, driver output stage; External: isolation, signal generation, main DC decoupling.

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Integration of the gate driver – 2

Dead-time Dead-time Level-shifter Buffer Buffer Dead-time Dead-time Level-shifter Buffer Buffer

Vbus OUT GND High-side gate driver Low-side gate driver DC DC DC DC DC DC DC DC DC DC DC DC PWM generator

Included: Power devices, small DC decoupling, driver output stage; External: isolation, signal generation, main DC decoupling.

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Integration of the gate driver – 3

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Integration of the gate driver – 4

0.2 0.1 0.0 time [µs] 50 50 100 150 200 250 Vout [V] 50.0 50.1 50.2 time [µs]

◮ Fast rising time (15 ns) with little ringing; ◮ Operation proven up to 310°

C ambient!

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Low inductance packaging – 1

◮ Dies soldered to two DBC substrates to form a “sandwich”

module;

◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link

(busbar).

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Low inductance packaging – 1

◮ Dies soldered to two DBC substrates to form a “sandwich”

module;

◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link

(busbar).

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Low inductance packaging – 1

◮ Dies soldered to two DBC substrates to form a “sandwich”

module;

◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link

(busbar).

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Low inductance packaging – 1

◮ Dies soldered to two DBC substrates to form a “sandwich”

module;

◮ Power module clamped between heat-exchangers; ◮ Connection to DC capacitors using a low inductance link

(busbar).

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 2

◮ “top”

heat-exchanger;

◮ power modules ◮ “bottom”

heat-exchanger;

◮ driver boards; ◮ driver

interconects;

◮ driver cover ◮ capacitor board; ◮ power terminals; ◮ busbar; ◮ capacitor cover.

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Low inductance packaging – 3

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Low inductance packaging – 4

10.1 10.2 10.3 time [µs] 100 200 300 400 500 600 700 Vout [V] 11.7 11.8 11.9 time [µs]

◮ Switching speed limited by switches (Si IGBTs, SiC

diodes);

◮ No ringing measured at the terminals of the modules; ◮ DC link inductance estimated at 10 nH.

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Integration of common-mode filtering – 1

◮ Include some common-mode filtering directly inside the

power module;

◮ Offers a short path to common-mode perturbations; ◮ Necessary with fast switching devices.

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Integration of common-mode filtering – 2

◮ 2 × 6 nF capacitors in the

power module;

◮ Connected to ground through

a damping resistor;

◮ External EMC filter for low

frequency.

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Integration of common-mode filtering – 2

◮ 2 × 6 nF capacitors in the

power module;

◮ Connected to ground through

a damping resistor;

◮ External EMC filter for low

frequency.

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Integration of common-mode filtering – 3

0.0 0.1 0.2 0.3 time [µs] 50 50 100 150 200 250 300 350 400 Vout [V] 24.5 24.6 time [µs]

With 6nF CCM Without integrated CCM

◮ Switching speed not altered by integrated common-mode

filtering.

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Outline Introduction Analysis of the switching cell Design improvements Integration of the gate driver Low inductance packaging Integration of common-mode filtering Conclusion

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Conclusion

◮ Silicon Carbide devices enables faster switches than Si ◮ Current packaging technologies must be adapted

accordingly

◮ By designing intrinsically-low-inductance packages ◮ Sandwich modules ◮ PCB-embedded circuit ◮ interconnects with laminated busbars ◮ By integrating more functions, even with standard

technology

◮ Filtering and decoupling ◮ Gate drives close to the devices

◮ Boundaries between module and converter less clear

◮ Design must be performed at die level. 27 / 28

Conclusion

◮ Silicon Carbide devices enables faster switches than Si ◮ Current packaging technologies must be adapted

accordingly

◮ By designing intrinsically-low-inductance packages ◮ Sandwich modules ◮ PCB-embedded circuit ◮ interconnects with laminated busbars ◮ By integrating more functions, even with standard

technology

◮ Filtering and decoupling ◮ Gate drives close to the devices

◮ Boundaries between module and converter less clear

◮ Design must be performed at die level. 27 / 28

Conclusion

◮ Silicon Carbide devices enables faster switches than Si ◮ Current packaging technologies must be adapted

accordingly

◮ By designing intrinsically-low-inductance packages ◮ Sandwich modules ◮ PCB-embedded circuit ◮ interconnects with laminated busbars ◮ By integrating more functions, even with standard

technology

◮ Filtering and decoupling ◮ Gate drives close to the devices

◮ Boundaries between module and converter less clear

◮ Design must be performed at die level. 27 / 28

Conclusion

◮ Silicon Carbide devices enables faster switches than Si ◮ Current packaging technologies must be adapted

accordingly

◮ By designing intrinsically-low-inductance packages ◮ Sandwich modules ◮ PCB-embedded circuit ◮ interconnects with laminated busbars ◮ By integrating more functions, even with standard

technology

◮ Filtering and decoupling ◮ Gate drives close to the devices

◮ Boundaries between module and converter less clear

◮ Design must be performed at die level. 27 / 28

Conclusion

◮ Silicon Carbide devices enables faster switches than Si ◮ Current packaging technologies must be adapted

accordingly

◮ By designing intrinsically-low-inductance packages ◮ Sandwich modules ◮ PCB-embedded circuit ◮ interconnects with laminated busbars ◮ By integrating more functions, even with standard

technology

◮ Filtering and decoupling ◮ Gate drives close to the devices

◮ Boundaries between module and converter less clear

◮ Design must be performed at die level. 27 / 28

Thank you for your attention,

cyril.buttay@insa-lyon.fr

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