Home assignment #2 Using spreadsheet to verify comparator logic 2015 - PowerPoint PPT Presentation

Home assignment #2 Using spreadsheet to verify comparator logic 2015

Spreadsheet template b>a, hence cout=0 A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 116 <<<<< 0<NUMBER<256 A>B?? NO a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 invert logic 0 0 0 1 1 0 1 1 0 CIN COUT COUT<<<<<< Comparator result: A>B? NO Both results are equal? YES 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 2

Spreadsheet template a>b, hence cout=1 A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 3 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 0 1 0 0 1 0 invert logic 1 1 1 1 1 0 0 0 0 CIN COUT COUT<<<<<< Comparator result: A>B? YES Both results are equal? YES a 6 >b 6 already in very significant bit. Correct cout is available very early, but we still have to wait for all bits to ripple from cin to cout. 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 3

Spreadsheet template a>b, hence cout=1 A= 1 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 0 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 invert logic 1 1 1 1 1 1 1 1 0 CIN COUT COUT<<<<<< Comparator result: A>B? YES Both results are equal? YES a 0 >b 0 in least significant bit. Correct cout is not available until carry generated in bit cell zero has rippled through all bit cells. 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 4

LSB to MSB or vice versa? tpd is worst case delay! Result available late if a 0 >b 0 (and all other bits are equal) Result available early if a 6 >b 6 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 5

Spreadsheet template A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 3 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 0 1 0 0 1 0 invert logic CIN COUT 1 1 1 1 1 0 0 0 0 COUT<<<<<< Comparator result: A>B? YES Both results are equal? YES Using same logic cell going downwards does not work! CIN COUT 0 0 1 1 1 1 1 0 0 Maybe it works with improved logic cell? Alternativ template for carry rippling from MSB to LSB CIN COUT 0 0 1 1 1 1 1 1 1 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 6

Spreadsheet template A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 116 <<<<< 0<NUMBER<256 A>B?? NO a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 invert logic CIN COUT 0 0 0 1 1 0 1 1 0 COUT<<<<<< Comparator result: A>B? NO Both results are equal? YES Maybe it works with improved logic cell? No, not for these inputs! Alternativ template for carry rippling from MSB to LSB CIN COUT 0 0 0 0 0 1 1 1 1 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 7

Spreadsheet template Example 1: a=89 and b=84. >>> cout=1 A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 84 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 invert logic CIN COUT 1 1 1 1 1 0 1 1 0 COUT<<<<<< Comparator result: A>B? YES Both results are equal? YES To go downwards in significance we must keep track of two rippling carries, one for a i >b i (G) and one for a i =b i (E). More complicated! G E 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 COUT CIN 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 8

Spreadsheet template Example 2: a=89 and b=116. >>> cout=0 A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 116 <<<<< 0<NUMBER<256 A>B?? NO a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 1 1 invert logic CIN COUT 0 0 0 1 1 0 1 1 0 COUT<<<<<< Comparator result: A>B? NO Both results are equal? YES G E 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 0 COUT CIN 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 9

Bitcell architecture Now, let us have a look at bit cell architecture and performance! cout cout cin 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 10

Bitcell netlist Typical hand ‐ in solution picked at random 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 11

MOSFET sizing Size inverter MOSFETs for equal driving capability (same effective resistance)! This PMOSFET can only deliver X X X X But making PMOSFET twice as half the current that the wide makes IDSAT,P =IDSAT,N NMOSFET can sink. For same width >> IDSAT,P = IDSAT,N/2 X X IDSAT,N IDSAT,N X X X X 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 12

MOSFET sizing But now compare capacitances! X X X X drain cap: pC drain cap: 2pC gate cap: C X X gate cap: 2C gate cap: C gate cap: C X X X X drain cap: pC drain cap: pC 2C 2pC 3C 3pC 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 13

Now size MOSFETs for same R in all pull ‐ up and pull ‐ down paths 6 6 6 6 6 6 2 Parasitic output cap=18pC 3pC 3C 1 2 2 2 2 2 2 Cin input cap = 16C 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 14

Delay calculation For simplicity: assume p =1 td=13*5ps=65 ps td1 td2 COUT CIN 16C 16C 3C 3C 18C td1=0.7*3RC(18/3+3/3)=5 ps*7=35 ps td2=0.7*3RC(3/3+16/3)=5 ps*6=30 ps 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 15

A better design with shorter delay For simplicity: assume p =1 td1=25 ps td2=15 ps COUT CIN 6C 12C 3C 3C 6C td=(4+1+1+2)*5ps=40 ps How to achieve this? This is almost 40% less delay! 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 16

Improved schematic! AB 4 4 4 00 10 11 01 0 0 1 0 0 CIN 1 1 1 1 0 4 4 Please, note how symmetric the COUT COUT Karnaugh map is! That is why pull ‐ up and pull ‐ 2 CIN 2 down networks can be made symmetric! 2 2 2 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 17

More on delay on Tuesday Any questions? 2015 ‐ 09 ‐ 10 MCC091 ‐ Home assignments 1 and 2 18