Home assignment #2 Using spreadsheet to verify comparator logic 2015 - - PowerPoint PPT Presentation

Home assignment #2

Using spreadsheet to verify comparator logic 2015

Spreadsheet template

A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 116 <<<<< 0<NUMBER<256 A>B?? NO a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< NO CIN COUT

b>a, hence cout=0

2015‐09‐10 MCC091 ‐ Home assignments 1 and 2 2

Spreadsheet template

A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 3 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< YES CIN COUT

a6>b6 already in very significant bit. Correct cout is available very early, but we still have to wait for all bits to ripple from cin to cout. a>b, hence cout=1

2015‐09‐10 MCC091 ‐ Home assignments 1 and 2 3

Spreadsheet template

a0>b0 in least significant bit. Correct cout is not available until carry generated in bit cell zero has rippled through all bit cells.

A= 1 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< YES CIN COUT

a>b, hence cout=1

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LSB to MSB or vice versa?

Result available early if a6>b6 Result available late if a0>b0 (and all other bits are equal)

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tpd is worst case delay!

Spreadsheet template

A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 3 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< YES CIN COUT 1 1 1 1 1 CIN COUT Alternativ template for carry rippling from MSB to LSB 1 1 1 1 1 1 1 CIN COUT

Using same logic cell going downwards does not work! Maybe it works with improved logic cell?

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Spreadsheet template

A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 116 <<<<< 0<NUMBER<256 A>B?? NO a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< NO CIN COUT Alternativ template for carry rippling from MSB to LSB 1 1 1 1 CIN COUT

Maybe it works with improved logic cell? No, not for these inputs!

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Spreadsheet template

A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 84 <<<<< 0<NUMBER<256 A>B?? YES a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< YES CIN COUT G E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CIN COUT

To go downwards in significance we must keep track of two rippling carries, one for ai>bi (G) and one for ai=bi (E). More complicated! Example 1: a=89 and b=84. >>> cout=1

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Spreadsheet template

A= 89 <<<<< ENTER TWO NUMBERS>0 CONTROL SIGNAL: 1 B= 116 <<<<< 0<NUMBER<256 A>B?? NO a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 invert logic 1 1 1 1 Comparator result: A>B? Both results are equal? YES COUT<<<<<< NO CIN COUT G E 1 1 1 1 1 1 1 1 1 CIN COUT

Example 2: a=89 and b=116. >>> cout=0

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Bitcell architecture

Now, let us have a look at bit cell architecture and performance! cout cout cin

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Bitcell netlist

Typical hand‐in solution picked at random

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MOSFET sizing

X X X X

This PMOSFET can only deliver half the current that the NMOSFET can sink. For same width >> IDSAT,P = IDSAT,N/2 IDSAT,N

X

IDSAT,N

X X X X X

But making PMOSFET twice as wide makes IDSAT,P =IDSAT,N Size inverter MOSFETs for equal driving capability (same effective resistance)!

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MOSFET sizing

X X

But now compare capacitances!

X X

gate cap: C drain cap: pC gate cap: C drain cap: pC 2C 2pC

X X X

gate cap: C drain cap: pC gate cap: 2C drain cap: 2pC

X X X

3C 3pC

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Now size MOSFETs for same R in all pull‐up and pull‐down paths

2 2 2 2 2 2 6 6 6 6 6 6 1 2 Parasitic output cap=18pC 3C 3pC Cin input cap = 16C

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Delay calculation

td1=0.7*3RC(18/3+3/3)=5 ps*7=35 ps td2=0.7*3RC(3/3+16/3)=5 ps*6=30 ps td=13*5ps=65 ps 16C 18C 3C 3C 16C For simplicity: assume p=1

CIN

td1 td2

COUT

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A better design with shorter delay

td=(4+1+1+2)*5ps=40 ps This is almost 40% less delay! 6C How to achieve this? 6C 12C 3C 3C For simplicity: assume p=1 td1=25 ps td2=15 ps

CIN COUT

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Improved schematic!

2 4 2 2 2 2 4 4 4 4

CIN COUT Please, note how symmetric the COUT Karnaugh map is! That is why pull‐up and pull‐ down networks can be made symmetric!

00 10 11 01 1 1 1 1 1 AB CIN

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More on delay on Tuesday Any questions?

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